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MICROMIPS ISA Reference		MD00594-2B-microMIPS64-AFP-6.05
ABS.S ft, fs	microMIPS	Floating Point Absolute Value
ABS.D ft, fs	microMIPS	Floating Point Absolute Value
ADD.S fd, fs, ft	microMIPS	Floating Point Add
ADD.D fd, fs, ft	microMIPS	Floating Point Add
ADDIUPC rt,immediate	microMIPS32 Release 6	Add Immediate to PC (unsigned - non-trapping)
ADDIUR1SP rd, decoded_immediate_value	microMIPS	Add Immediate Unsigned Word One Register (16-bit instr size)
ADDIUR2 rd, rs1, decoded_immediate_value	microMIPS	Add Immediate Unsigned Word Two Registers (16-bit instr size)
ADDIU rt, rs, immediate	microMIPS	Add Immediate Unsigned Word
ADDIUS5 rd, decoded_immediate_value	microMIPS	Add Immediate Unsigned Word 5-Bit Register Select (16-bit instr size)
ADDIUSP decoded_immediate_value	microMIPS	Add Immediate Unsigned Word to Stack Pointer(16-bit instr size)
ADD rd, rs, rt	microMIPS	Add Word
ADDU16 rd, rs, rt	microMIPS	Add Unsigned Word (16-bit instr size)
ADDU rd, rs, rt	microMIPS	Add Unsigned Word
ALIGN rd,rs,rt,bp	microMIPS32 Release 6	Concatenate two GPRs, and extract a contiguous subset at a byte position
DALIGN rd,rs,rt,bp	microMIPS64 Release 6	Concatenate two GPRs, and extract a contiguous subset at a byte position
ALUIPC rt,immediate	microMIPS32 Release 6	Aligned Add Upper Immediate to PC
AND16 rt, rs	microMIPS	To do a bitwise logical AND
ANDI16 rd, rs, decoded_immediate_value	microMIPS	And Immediate (16-bit instr size)
ANDI rt, rs, immediate	microMIPS	and immediate
AND rd, rs, rt	microMIPS	and
AUI rt, rs immediate	microMIPS32 Release 6	Add Upper Immediate
DAUI rt, rs immediate	microMIPS64 Release 6	Doubleword Add Upper Immediate
DAHI rs, rs immediate	microMIPS64 Release 6	Doubleword Add Higher Immediate
DATI rs, rs immediate	microMIPS64 Release 6	Doubleword Add Top Immediate
AUIPC rt, immediate	microMIPS32 Release 6	Add Upper Immediate to PC
BALC offset	microMIPS32 Release 6	Branch and Link, Compact
BC16 offset	microMIPS Release 6	Unconditional Branch Compact (16-bit instr size)
BC1EQZC ft, offset	microMIPS32 Release 6	Branch if Coprocessor 1 (FPU) Register Bit 0 is Equal to Zero
BC1NEZC ft, offset	microMIPS32 Release 6	Branch if Coprocessor 1 (FPR) Register Bit 0 is Not Equal to Zero
BC2EQZC ct, offset	microMIPS32 Release 6	Branch if Coprocessor 2 Condition (Register) is Equal to Zero
BC2NEZC ct, offset	microMIPS32 Release 6	Branch if Coprocessor 2 Condition (Register) is Not Equal to Zero
BC offset	microMIPS32 Release 6	Branch, Compact
BEQZC16 rs, offset	microMIPS Release 6	Branch on Equal to Zero Compact (16-bit instr size)
BITSWAP rd,rt	microMIPS32 Release 6	Swaps (reverses) bits in each byte
DBITSWAP rd,rt	microMIPS64 Release 6	Swaps (reverses) bits in each byte
BNEZC16 rs, offset	microMIPS Release 6	Branch on Not Equal to Zero Compact (16-bit instr size)
BOVC rt,rs, offset	microMIPS32 Release 6	Detect overflow for add (signed 32 bits) and branch if overflow.
BNVC rt,rs, offset	microMIPS32 Release 6	Detect overflow for add (signed 32 bits) and branch if no overflow.
BREAK	microMIPS	Breakpoint
BREAK16	microMIPS	Breakpoint
BEQC rs, rt, offset	microMIPS32 Release 6	Equal/Not-Equal register-register compare and branch with 16-bit offset:
BNEC rs, rt, offset	microMIPS32 Release 6	Equal/Not-Equal register-register compare and branch with 16-bit offset:
BLTC rs, rt, offset	microMIPS32 Release 6	Signed register-register compare and branch with 16-bit offset:
BGEC rs, rt, offset	microMIPS32 Release 6	Signed register-register compare and branch with 16-bit offset:
BLTUC rs, rt, offset	microMIPS32 Release 6	Unsigned register-register compare and branch with 16-bit offset:
BGEUC rs, rt, offset	microMIPS32 Release 6	Unsigned register-register compare and branch with 16-bit offset:
BGTC rt, rs, offset	Assembly Idiom, microMIPS32 Release 6	Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BLEC rt, rs, offset	Assembly Idiom, microMIPS32 Release 6	Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BGTUC rt, rs, offset	Assembly Idiom, microMIPS32 Release 6	Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BLEUC rt, rs, offset	Assembly Idiom, microMIPS32 Release 6	Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BLTZC rt, offset	microMIPS32 Release 6	Signed Compare register to Zero and branch with 16-bit offset:
BLEZC rt, rs, offset	microMIPS32 Release 6	Signed Compare register to Zero and branch with 16-bit offset:
BGEZC rt, offset	microMIPS32 Release 6	Signed Compare register to Zero and branch with 16-bit offset:
BGTZC rt, rs, offset	microMIPS32 Release 6	Signed Compare register to Zero and branch with 16-bit offset:
BEQZC rt, rs, offset	microMIPS32 Release 6	Equal/Not-equal Compare register to Zero and branch with 21-bit offset:
BNEZC rt, rs, offset	microMIPS32 Release 6	Equal/Not-equal Compare register to Zero and branch with 21-bit offset:
BLEZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is less than or equal to zero
BGEZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is greater than or equal to zero
BGTZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is greater than zero
BLTZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is less than to zero
BEQZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is equal to zero
BNEZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is not equal to zero
CACHEE op, offset(base)	microMIPS	Perform Cache Operation EVA
CACHE op, offset(base)	microMIPS	Perform Cache Operation
CEIL.L.S ft, fs	MIPS64, microMIPS	Fixed Point Ceiling Convert to Long Fixed Point
CEIL.L.D ft, fs	MIPS64, microMIPS	Fixed Point Ceiling Convert to Long Fixed Point
CEIL.W.S ft, fs	microMIPS	Floating Point Ceiling Convert to Word Fixed Point
CEIL.W.D ft, fs	microMIPS	Floating Point Ceiling Convert to Word Fixed Point
CFC1 rt, fs	microMIPS	Move Control Word From Floating Point
CFC2 rt, Impl	microMIPS	Move Control Word From Coprocessor 2
CLASS fd, fs, fmt	microMIPS32 Release 6	Scalar Floating-Point Class Mask
CLASS.S fd,fs	microMIPS32 Release 6	Scalar Floating-Point Class Mask
CLASS.D fd,fs	microMIPS32 Release 6	Scalar Floating-Point Class Mask
CLO rt, rs	microMIPS	Count Leading Ones in Word
CLZ rt, rs	microMIPS	Count Leading Zeros in Word
CMP.condn.S fd, fs, ft	microMIPS32 Release 6	Floating Point Compare Setting Mask
CMP.condn.D fd, fs, ft	microMIPS32 Release 6	Floating Point Compare Setting Mask
COP2 func	microMIPS	Coprocessor Operation to Coprocessor 2
CRC32B rt, rs, rt	microMIPS32 Release 6	Generate CRC with reversed polynomial 0xEDB88320
CRC32H rt, rs, rt	microMIPS32 Release 6	Generate CRC with reversed polynomial 0xEDB88320
CRC32W rt, rs, rt	microMIPS32 Release 6	Generate CRC with reversed polynomial 0xEDB88320
CRC32D rt, rs, rt	microMIPS64 Release 6	Generate CRC with reversed polynomial 0xEDB88320
CRC32CB rt, rs, rt	microMIPS32 Release 6	Generate CRC with reversed polynomial 0x82F63B78
CRC32CH rt, rs, rt	microMIPS32 Release 6	Generate CRC with reversed polynomial 0x82F63B78
CRC32CW rt, rs, rt	microMIPS32 Release 6	Generate CRC with reversed polynomial 0x82F63B78
CRC32CD rt, rs, rt	microMIPS64 Release 6	Generate CRC with reversed polynomial 0x82F63B78
CTC1 rt, fs	microMIPS	Move Control Word to Floating Point
CTC2 rt, Impl	microMIPS	Move Control Word to Coprocessor 2
CVT.D.S ft, fs	microMIPS	Floating Point Convert to Double Floating Point
CVT.D.W ft, fs	microMIPS	Floating Point Convert to Double Floating Point
CVT.D.L ft, fs	MIPS64, microMIPS	Floating Point Convert to Double Floating Point
CVT.L.S ft, fs	MIPS64, microMIPS	Floating Point Convert to Long Fixed Point
CVT.L.D ft, fs	MIPS64, microMIPS	Floating Point Convert to Long Fixed Point
CVT.S.D ft, fs	microMIPS	Floating Point Convert to Single Floating Point
CVT.S.W ft, fs	microMIPS	Floating Point Convert to Single Floating Point
CVT.S.L ft, fs	MIPS64, microMIPS	Floating Point Convert to Single Floating Point
CVT.W.S ft, fs	microMIPS	Floating Point Convert to Word Fixed Point
CVT.W.D ft, fs	microMIPS	Floating Point Convert to Word Fixed Point
DADDIU rt, rs, immediate	microMIPS64	Doubleword Add Immediate Unsigned
DADD rd, rs, rt	microMIPS64	Doubleword Add
DADDU rd, rs, rt	microMIPS64	Doubleword Add Unsigned
DCLO rd, rs	microMIPS64	Count Leading Ones in Doubleword
DCLZ rd, rs	microMIPS64	Count Leading Zeros in Doubleword
DERET	microMIPS32, EJTAG	Debug Exception Return
DEXTM rt, rs, pos, size	microMIPS	Doubleword Extract Bit Field Middle
DEXT rt, rs, pos, size	microMIPS64	Doubleword Extract Bit Field
DI	microMIPS	Disable Interrupts
DI rs	microMIPS	Disable Interrupts
DINSM rt, rs, pos, size	microMIPS64	Doubleword Insert Bit Field Middle
DINS rt, rs, pos, size	microMIPS64	Doubleword Insert Bit Field
DINSU rt, rs, pos, size	microMIPS64	Doubleword Insert Bit Field Upper
DIV.S fd, fs, ft	microMIPS	Floating Point Divide
DIV.D fd, fs, ft	microMIPS	Floating Point Divide
DIV rd,rs,rt	microMIPS32 Release 6	Divide Words Signed
MOD rd,rs,rt	microMIPS32 Release 6	Modulo Words Signed
DIVU rd,rs,rt	microMIPS32 Release 6	Divide Words Unsigned
MODU rd,rs,rt	microMIPS32 Release 6	Modulo Words Unsigned
DDIV rd,rs,rt	microMIPS64 Release 6	Divide Doublewords Signed
DMOD rd,rs,rt	microMIPS64 Release 6	Modulo Doublewords Signed
DDIVU rd,rs,rt	microMIPS64 Release 6	Divide Doublewords Unsigned
DMODU rd,rs,rt	microMIPS64 Release 6	Modulo Doublewords Unsigned
DMFC0 rt, rs	microMIPS64	Doubleword Move from Coprocessor 0
DMFC0 rt, rs, sel	microMIPS64	Doubleword Move from Coprocessor 0
DMFC1 rt,fs	microMIPS64	Doubleword Move from Floating Point
DMFC2 rt, rd	microMIPS64	Doubleword Move from Coprocessor 2
DMFC2, rt, rd, sel	microMIPS64	Doubleword Move from Coprocessor 2
DMTC0 rt, rs	microMIPS64	Doubleword Move to Coprocessor 0
DMTC0 rt, rs, sel	microMIPS64	Doubleword Move to Coprocessor 0
DMTC1 rt, fs	microMIPS64	Doubleword Move to Floating Point
DMTC2 rt,Impl	microMIPS64	Doubleword Move to Coprocessor 2
DMTC2 rt, Impl, sel	microMIPS64	Doubleword Move to Coprocessor 2
DROTR32 rt, rs, sa	microMIPS64	Doubleword Rotate Right Plus 32
DROTR rt, rs, sa	microMIPS64	Doubleword Rotate Right
DROTRV rd, rt, rs	microMIPS64	Doubleword Rotate Right Variable
DSBH rt, rs	microMIPS64	Doubleword Swap Bytes Within Halfwords
DSHD rt, rs	microMIPS64	Doubleword Swap Halfwords Within Doublewords
DSLL32 rt, rs, sa	microMIPS64	Doubleword Shift Left Logical Plus 32
DSLL rt, rs, sa	microMIPS64	Doubleword Shift Left Logical
DSLLV rd, rt, rs	microMIPS64	Doubleword Shift Left Logical Variable
DSRA32 rt, rs, sa	microMIPS64	Doubleword Shift Right Arithmetic Plus 32
DSRA rt, rs, sa	microMIPS64	Doubleword Shift Right Arithmetic
DSRAV rd, rt, rs	microMIPS64	Doubleword Shift Right Arithmetic Variable
DSRL32 rt, rs, sa	microMIPS64	Doubleword Shift Right Logical Plus 32
DSRL rt, rs, sa	microMIPS64	Doubleword Shift Right Logical
DSRLV rd, rt, rs	microMIPS64	Doubleword Shift Right Logical Variable
DSUB rd, rs, rt	microMIPS64	Doubleword Subtract
DSUBU rd, rs, rt	microMIPS64	Doubleword Subtract Unsigned
DVP rt	microMIPS Release 6	Disable Virtual Processor
EHB	microMIPS	Execution Hazard Barrier
EI	microMIPS	Enable Interrupts
EI rs	microMIPS	Enable Interrupts
ERET	microMIPS	Exception Return
ERETNC	microMIPS Release 5	Exception Return No Clear
EVP rt	microMIPS Release 6	Enable Virtual Processor
EXT rt, rs, pos, size	microMIPS	Extract Bit Field
FLOOR.L.S ft, fs	MIPS64, microMIPS	Floating Point Floor Convert to Long Fixed Point
FLOOR.L.D ft, fs	MIPS64, microMIPS	Floating Point Floor Convert to Long Fixed Point
FLOOR.W.S ft, fs	microMIPS	Floating Point Floor Convert to Word Fixed Point
FLOOR.W.D ft, fs	microMIPS	Floating Point Floor Convert to Word Fixed Point
GINVI rs	microMIPS Release 6	Global Invalidate Instruction Cache
GINVT rs, type	microMIPS Release 6	Global Invalidate TLB
INS rt, rs, pos, size	microMIPS	Insert Bit Field
JALRC.HB rt, rs	microMIPS Release 6	Jump and Link Register Compact with Hazard Barrier
JALRC16 rs	microMIPS Release 6	Jump and Link Register Compact (16-bit instr size)
JALRC rt, rs	microMIPS Release 6	Jump and Link Register Compact
JIALC rt, offset	microMIPS32 Release 6	Jump Indexed and Link, Compact
JIC rt, offset	microMIPS32 Release 6	Jump Indexed, Compact
JRC16 rs	microMIPS	Jump Register Compact (16-bit instr size)
JRCADDIUSP decoded_immediate	microMIPS Release 6	Jump Register Compact, Adjust Stack Pointer (16-bit)
LBE rt, offset(base)	microMIPS	Load Byte EVA
LB rt, offset(base)	microMIPS	Load Byte
LBU16 rt, decoded_offset(base)	microMIPS	Load Byte Unsigned (16-bit instr size)
LBUE rt, offset(base)	microMIPS	Load Byte Unsigned EVA
LBU rt, offset(base)	microMIPS	Load Byte Unsigned
LDC1 ft, offset(base)	microMIPS	Load Doubleword to Floating Point
LDC2 rt, offset(base)	microMIPS	Load Doubleword to Coprocessor 2
LDM {sregs, } {ra}, offset(base)	microMIPS	Load Doubleword Multiple
LDPC rt, offset	microMIPS64 Release 6	Load Doubleword PC-relative
LDP rd, offset(base)	microMIPS	Load Doubleword Pair
LD rt, offset(base)	microMIPS64	Load Doubleword
LHE rt, offset(base)	microMIPS	Load Halfword EVA
LH rt, offset(base)	microMIPS	Load Halfword
LHU16 rt, left_shifted_offset(base)	microMIPS	Load Halfword Unsigned (16-bit instr size)
LHUE rt, offset(base)	microMIPS	Load Halfword Unsigned EVA
LHU rt, offset(base)	microMIPS	Load Halfword Unsigned
LI16 rd, decoded_immediate	microMIPS	Load Immediate Word (16-bit instr size)
LLDP rt, rd, (base)	microMIPS64 Release 6	Load Linked DoubleWord Paired
LLE rt, offset(base)	microMIPS	Load Linked Word EVA
LL rt, offset(base)	microMIPS	Load Linked Word
LLWPE rt, rd, (base)	microMIPS Release 6	Load Linked Word Paired EVA
LLWP rt, rd, (base)	microMIPS Release 6	Load Linked Word Paired
LSA rt, rs, rd, sa	microMIPS32 Release 6	Load Scaled Address, Doubleword Load Scaled Address
DLSA rt, rs,rd, sa	microMIPS64 Release 6	Load Scaled Address, Doubleword Load Scaled Address
LUI rt, immediate	microMIPS, Assembly Idiom Release 6	Load Upper Immediate
LW16 rt, left_shifted_offset(base)	microMIPS	Load Word (16-bit instr size)
LWC1 ft, offset(base)	microMIPS	Load Word to Floating Point
LWC2 rt, offset(base)	microMIPS	Load Word to Coprocessor 2
LWE rt, offset(base)	microMIPS	Load Word EVA
LW16 rt, left_shifted_offset(gp)	microMIPS	Load Word from Global Pointer (16-bit instr size)
LWM16 s0, {s1, {s2, {s3,}}} ra, left_shifted_offset(sp)	microMIPS	Load Word Multiple (16-bit)
LWM32 {sre16, } {ra}, offset(base)	microMIPS	Load Word Multiple
LWPC rt, offset	microMIPS32 Release 6	Load Word PC-relative
LWP rd, offset(base)	microMIPS	Load Word Pair
LW rt, offset(base)	microMIPS	Load Word
LW16 rt, left_shifted_offset(sp)	microMIPS	Load Word from Stack Pointer (16-bit instr size)
LWUPC rt, offset	microMIPS64 Release 6	Load Word Unsigned PC-relative
LWU rt, offset(base)	microMIPS64	Load Word Unsigned
MADDF.S fd, fs, ft	microMIPS32 Release 6	Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MADDF.D fd, fs, ft	microMIPS32 Release 6	Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MSUBF.S fd, fs, ft	microMIPS32 Release 6	Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MSUBF.D fd, fs, ft	microMIPS32 Release 6	Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MAX.S fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MAX.D fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MAXA.S fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MAXA.D fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MIN.S fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MIN.D fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MINA.S fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MINA.D fd,fs,ft	microMIPS32 Release 6	Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MFC0 rt, rs	microMIPS	Move from Coprocessor 0
MFC0 rt, rs, sel	microMIPS	Move from Coprocessor 0
MFC1 rt, fs	microMIPS	Move Word From Floating Point
MFC2 rt, Impl	microMIPS	Move Word From Coprocessor 2
MFHC0 rt, rs	microMIPS Release 5	Move from High Coprocessor 0
MFHC0 rt, rs, sel	microMIPS Release 5	Move from High Coprocessor 0
MFHC1 rt, fs	microMIPS	Move Word From High Half of Floating Point Register
MFHC2 rt, Impl	microMIPS	Move Word From High Half of Coprocessor 2 Register
MOV.S ft, fs	microMIPS	Floating Point Move
MOV.D ft, fs	microMIPS	Floating Point Move
MOVE16 rd, rs	microMIPS	Move Register (16-bit instr size)
MOVEP rd, re, rs, rt	microMIPS	Move a Pair of Registers
MTC0 rt, rs	microMIPS	Move to Coprocessor 0
MTC0 rt, rs, sel	microMIPS	Move to Coprocessor 0
MTC1 rt, fs	microMIPS	Move Word to Floating Point
MTC2 rt, Impl	microMIPS	Move Word to Coprocessor 2
MTHC0 rt, rs	microMIPS Release 5	Move to High Coprocessor 0
MTHC0 rt, rs, sel	microMIPS Release 5	Move to High Coprocessor 0
MTHC1 rt, fs	microMIPS	Move Word to High Half of Floating Point Register
MTHC2 rt, Impl	microMIPS	Move Word to High Half of Coprocessor 2 Register
MUL.S fd, fs, ft	microMIPS	Floating Point Multiply
MUL.D fd, fs, ft	microMIPS	Floating Point Multiply
MUL rd,rs,rt	microMIPS32 Release 6	Multiply Words Signed, Low Word
MUH rd,rs,rt	microMIPS32 Release 6	Multiply Words Signed, High Word
MULU rd,rs,rt	microMIPS32 Release 6	Multiply Words Unsigned, Low Word
MUHU rd,rs,rt	microMIPS32 Release 6	Multiply Words Unsigned, High Word
DMUL rd,rs,rt	microMIPS64 Release 6	Multiply Doublewords Signed, Low Doubleword
DMUH rd,rs,rt	microMIPS64 Release 6	Multiply Doublewords Signed, High Doubleword
DMULU rd,rs,rt	microMIPS64 Release 6	Multiply Doublewords Unsigned, Low Doubleword
DMUHU rd,rs,rt	microMIPS64 Release 6	Multiply Doublewords Unsigned, High Doubleword
NEG.S ft, fs	microMIPS	Floating Point Negate
NEG.D ft, fs	microMIPS	Floating Point Negate
NOP	Assembly Idiom microMIPS	No Operation
NOR rd, rs, rt	microMIPS	Not Or
NOT16 rt, rs	microMIPS	Invert (16-bit instr size)
OR16 rt, rs	microMIPS32	Or (16-bit instr size)
ORI rt, rs, immediate	microMIPS	Or Immediate
OR rd, rs, rt	microMIPS	Or
PAUSE	microMIPS	Wait for the LLBit to clear.
PREFE hint,offset(base)	microMIPS	Prefetch EVA
PREF hint,offset(base)	microMIPS	Prefetch
RDHWR rt,rs,sel	microMIPS	Read Hardware Register
RDPGPR rt, rs	microMIPS	Read GPR from Previous Shadow Set
RECIP.S ft, fs	microMIPS	Reciprocal Approximation
RECIP.D ft, fs	microMIPS	Reciprocal Approximation
RINT fd, fs	microMIPS32 Release 6	Floating-Point Round to Integral
ROTR rt, rs, sa	SmartMIPS Crypto, microMIPS	Rotate Word Right
ROTRV rd, rt, rs	SmartMIPS Crypto, microMIPS	Rotate Word Right Variable
ROUND.L.S ft, fs	microMIPS	Floating Point Round to Long Fixed Point
ROUND.L.D ft, fs	microMIPS	Floating Point Round to Long Fixed Point
ROUND.W.S ft, fs	microMIPS	Floating Point Round to Word Fixed Point
ROUND.W.D ft, fs	microMIPS	Floating Point Round to Word Fixed Point
RSQRT.S ft, fs	microMIPS	Reciprocal Square Root Approximation
RSQRT.D ft, fs	microMIPS	Reciprocal Square Root Approximation
SB16 rt, offset(base)	microMIPS	Store Byte (16-bit instr size)
SBE rt, offset(base)	microMIPS	Store Byte EVA
SB rt, offset(base)	microMIPS	Store Byte
SCDP rt, rd, (base)	microMIPS64 Release 6	Store Conditional DoubleWord Paired
SCD rt, offset(base)	microMIPS	Store Conditional Doubleword
SCE rt, offset(base)	microMIPS	Store Conditional Word EVA
SC rt, offset(base)	microMIPS	Store Conditional Word
SCWPE rt, rd, (base)	microMIPS Release 6	Store Conditional Word Paired EVA
SCWP rt, rd, (base)	microMIPS Release 6	Store Conditional Word Paired
SDBBP16 code	microMIPS32, EJTAG	Software Debug Breakpoint (16-bit instr size)
SDBBP code	microMIPS32, EJTAG	Software Debug Breakpoint
SDC1 ft, offset(base)	microMIPS	Store Doubleword from Floating Point
SDC2 rt, offset(base)	microMIPS	Store Doubleword from Coprocessor 2
SDM {sregs, } {ra}, offset(base)	microMIPS	Store Doubleword Multiple
SDP rd, offset(base)	microMIPS	Store Doubleword Pair
SD rt, offset(base)	microMIPS64	Store Doubleword
SEB rt, rs	microMIPS	Sign-Extend Byte
SEH rt, rs	microMIPS	Sign-Extend Halfword
SEL fd, fs, ft, fmt	microMIPS32 Release 6	Select floating point values with FPR condition
SELEQZ.S fd,fs,ft	microMIPS32 Release 6	Select floating point value or zero with FPR condition.
SELEQZ.D fd,fs,ft	microMIPS32 Release 6	Select floating point value or zero with FPR condition.
SELNEZ.S fd,fs,ft	microMIPS32 Release 6	Select floating point value or zero with FPR condition.
SELNEZ.D fd,fs,ft	microMIPS32 Release 6	Select floating point value or zero with FPR condition.
SELEQZ rd,rs,rt	microMIPS32 Release 6	Select integer GPR value or zero
SELNEZ rd,rs,rt	microMIPS32 Release 6	Select integer GPR value or zero
SH16 rt, left_shifted_offset(base)	microMIPS	Store Halfword (16-bit instr size)
SHE rt, offset(base)	microMIPS	Store Halfword EVA
SH rt, offset(base)	microMIPS	Store Halfword
SIGRIE code	MIPS32 Release 6	Signal Reserved Instruction Exception
SLL16 rd, rt, decoded_sa	microMIPS	Shift Word Left Logical (16-bit instr size)
SLL rt, rs, sa	microMIPS	Shift Word Left Logical
SLLV rd, rt, rs	microMIPS	Shift Word Left Logical Variable
SLTI rt, rs, immediate	microMIPS	Set on Less Than Immediate
SLTIU rt, rs, immediate	microMIPS	Set on Less Than Immediate Unsigned
SLT rd, rs, rt	microMIPS	Set on Less Than
SLTU rd, rs, rt	microMIPS	Set on Less Than Unsigned
SQRT.S ft, fs	MIPS32	Floating Point Square Root
SQRT.D ft, fs	MIPS32	Floating Point Square Root
SRA rt, rs, sa	microMIPS	Shift Word Right Arithmetic
SRAV rd, rt, rs	microMIPS	Shift Word Right Arithmetic Variable
SRL16 rd, rt, decoded_sa	microMIPS	Shift Word Right Logical (16-bit instr size)
SRL rt, rs, sa	microMIPS	Shift Word Right Logical
SRLV rd, rt, rs	microMIPS	Shift Word Right Logical Variable
SSNOP	microMIPS	Superscalar No Operation
SUB.S fd, fs, ft	microMIPS	Floating Point Subtract
SUB.D fd, fs, ft	microMIPS	Floating Point Subtract
SUB rd, rs, rt	microMIPS	Subtract Word
SUBU16 rd, rs, rt	microMIPS	Subtract Unsigned Word (16-bit instr size)
SUBU rd, rs, rt	microMIPS	Subtract Unsigned Word
SW16 rt, left_shifted_offset(base)	microMIPS	Store Word (16-bit instr size)
SWC1 ft, offset(base)	microMIPS	Store Word from Floating Point
MFHC0 rt, rs, sel	microMIPS Release 5	Move from High Coprocessor 0
SWC2 rt, offset(base)	microMIPS	Store Word from Coprocessor 2
SWE rt, offset(base)	microMIPS	Store Word EVA
SWM16 s0, {s1, {s2, {s3,}}} ra, left_shifted_offset(sp)	microMIPS	Store Word Multiple (16-bit)
SWM32 {sregs, } {ra}, offset(base)	microMIPS	Store Word Multiple
SWP rs1, offset(base)	microMIPS	Store Word Pair
SW rt, offset(base)	microMIPS	Store Word
SWSP rt, left_shifted_offset(base)	microMIPS	Store Word to Stack Pointer (16-bit instr size)
SYNCI offset(base)	microMIPS	Synchronize Caches to Make Instruction Writes Effective
SYNC stype	microMIPS	Synchronize Shared Memory
SYSCALL	microMIPS	System Call
TEQ rs, rt	microMIPS	Trap if Equal
TGE rs, rt	microMIPS	Trap if Greater or Equal
TGEU rs, rt	microMIPS	Trap if Greater or Equal Unsigned
TLBINV	microMIPS	TLB Invalidate
TLBINVF	microMIPS	TLB Invalidate Flush
TLBP	microMIPS	Probe TLB for Matching Entry
TLBR	microMIPS	Read Indexed TLB Entry
TLBWI	microMIPS	Write Indexed TLB Entry
TLBWR	microMIPS	Write Random TLB Entry
TLT rs, rt	microMIPS	Trap if Less Than
TLTU rs, rt	microMIPS	Trap if Less Than Unsigned
TNE rs, rt	microMIPS	Trap if Not Equal
TRUNC.L.S ft, fs	microMIPS	Floating Point Truncate to Long Fixed Point
TRUNC.L.D ft, fs	microMIPS	Floating Point Truncate to Long Fixed Point
TRUNC.W.S ft, fs	microMIPS	Floating Point Truncate to Word Fixed Point
TRUNC.W.D ft, fs	microMIPS	Floating Point Truncate to Word Fixed Point
WAIT	microMIPS	Enter Standby Mode
WRPGPR rt, rs	microMIPS	Write to GPR in Previous Shadow Set
WSBH rt, rs	microMIPS	Word Swap Bytes Within Halfwords
XOR16 rt, rs	microMIPS	Exclusive OR (16-bit instr size)
XORI rt, rs, immediate	microMIPS	Exclusive OR Immediate
XOR rd, rs, rt	microMIPS	Exclusive OR
MICROMIPS ASE-DSP ISA Reference		MD00765-2B-microMIPS64DSP-AFP-03.02
ABSQ_S.PH rdt, rts	microMIPSDSP	Find Absolute Value of Two Fractional Halfwords
ABSQ_S.QB rdt, rts	microMIPSDSP-R2	Find Absolute Value of Four Fractional Byte Values
ABSQ_S.W rdt, rts	microMIPSDSP	Find Absolute Value of Fractional Word
ADDQH.PH rd, rs, rt	microMIPSDSP-R2	Add Fractional Halfword Vectors And Shift Right to Halve Results
ADDQH_R.PH rd, rs, rt	microMIPSDSP-R2	Add Fractional Halfword Vectors And Shift Right to Halve Results
ADDQH.W rd, rs, rt	microMIPSDSP-R2	Add Fractional Words And Shift Right to Halve Results
ADDQH_R.W rd, rs, rt	microMIPSDSP-R2	Add Fractional Words And Shift Right to Halve Results
ADDQ.PH rd, rs, rt	microMIPSDSP	Add Fractional Halfword Vectors
ADDQ_S.PH rd, rs, rt	microMIPSDSP	Add Fractional Halfword Vectors
ADDQ_S.W rd, rs, rt	microMIPSDSP	Add Fractional Words
ADDSC rd, rs, rt	microMIPSDSP	Add Signed Word and Set Carry Bit
ADDUH.QB rd, rs, rt	microMIPSDSP-R2	Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results
ADDUH_R.QB rd, rs, rt	microMIPSDSP-R2	Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results
ADDU.PH rd, rs, rt	microMIPSDSP-R2	Unsigned Add Integer Halfwords
ADDU_S.PH rd, rs, rt	microMIPSDSP-R2	Unsigned Add Integer Halfwords
ADDU.QB rd, rs, rt	microMIPSDSP	Unsigned Add Quad Byte Vectors
ADDU_S.QB rd, rs, rt	microMIPSDSP	Unsigned Add Quad Byte Vectors
ADDWC rd, rs, rt	microMIPSDSP	Add Word with Carry Bit
APPEND rt, rs, sa	microMIPSDSP-R2	Left Shift and Append Bits to the LSB
BALIGN rt, rs, bp	microMIPSDSP-R2	Byte Align Contents from Two Registers
BITREV rdt, rts	microMIPSDSP	Bit-Reverse Halfword
BPOSGE32C offset	microMIPSDSP-R3	Branch on Greater Than or Equal To Value 32 in
BPOSGE32 offset	microMIPSDSP, removed in Release 6	Branch on Greater Than or Equal To Value 32 in
CMP.EQ.PH rs, rt	microMIPSDSP	Compare Vectors of Signed Integer Halfword Values
CMP.LT.PH rs, rt	microMIPSDSP	Compare Vectors of Signed Integer Halfword Values
CMP.LE.PH rs, rt	microMIPSDSP	Compare Vectors of Signed Integer Halfword Values
CMPGDU.EQ.QB rd, rs, rt	microMIPSDSP-R2	Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl
CMPGDU.LT.QB rd, rs, rt	microMIPSDSP-R2	Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl
CMPGDU.LE.QB rd, rs, rt	microMIPSDSP-R2	Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl
CMPGU.EQ.QB rd, rs, rt	microMIPSDSP	Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPGU.LT.QB rd, rs, rt	microMIPSDSP	Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPGU.LE.QB rd, rs, rt	microMIPSDSP	Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPU.EQ.QB rs, rt	microMIPSDSP	Compare Vectors of Unsigned Byte Values
CMPU.LT.QB rs, rt	microMIPSDSP	Compare Vectors of Unsigned Byte Values
CMPU.LE.QB rs, rt	microMIPSDSP	Compare Vectors of Unsigned Byte Values
DPA.W.PH ac, rs, rt	microMIPSDSP-R2	Dot Product with Accumulate on Vector Integer Halfword Elements
DPAQX_S.W.PH ac, rs, rt	microMIPSDSP-R2	Cross Dot Product with Accumulation on Fractional Halfword Elements
DPAQX_SA.W.PH ac, rs, rt	microMIPSDSP-R2	Cross Dot Product with Accumulation on Fractional Halfword Elements
DPAQ_S.W.PH ac, rs, rt	microMIPSDSP	Dot Product with Accumulation on Fractional Halfword Elements
DPAQ_SA.L.W ac, rs, rt	microMIPSDSP	Dot Product with Accumulate on Fractional Word Element
DPAU.H.QBL ac, rs, rt	microMIPSDSP	Dot Product with Accumulate on Vector Unsigned Byte Elements
DPAU.H.QBR ac, rs, rt	microMIPSDSP	Dot Product with Accumulate on Vector Unsigned Byte Elements
DPAX.W.PH ac, rs, rt	microMIPSDSP-R2	Cross Dot Product with Accumulate on Vector Integer Halfword Elements
DPS.W.PH ac, rs, rt	microMIPSDSP-R2	Dot Product with Subtract on Vector Integer Half-Word Elements
DPSQX_S.W.PH ac, rs, rt	microMIPSDSP-R2	Cross Dot Product with Subtraction on Fractional Halfword Elements
DPSQX_SA.W.PH ac, rs, rt	microMIPSDSP-R2	Cross Dot Product with Subtraction on Fractional Halfword Elements
DPSQ_S.W.PH ac, rs, rt	microMIPSDSP	Dot Product with Subtraction on Fractional Halfword Elements
DPSQ_SA.L.W ac, rs, rt	microMIPSDSP	Dot Product with Subtraction on Fractional Word Element
DPSU.H.QBL ac, rs, rt	microMIPSDSP	Dot Product with Subtraction on Vector Unsigned Byte Elements
DPSU.H.QBR ac, rs, rt	microMIPSDSP	Dot Product with Subtraction on Vector Unsigned Byte Elements
DPSX.W.PH ac, rs, rt	microMIPSDSP-R2	Cross Dot Product with Subtract on Vector Integer Halfword Elements
EXTPDP rt, ac, size	microMIPSDSP	Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos
EXTPDPV rt, ac, rs	microMIPSDSP	Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos
EXTP rt, ac, size	microMIPSDSP	Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR
EXTPV rt, ac, rs	microMIPSDSP	Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR
EXTRV.W rt, ac, rs	microMIPSDSP	Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_R.W rt, ac, rs	microMIPSDSP	Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_RS.W rt, ac, rs	microMIPSDSP	Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_S.H rt, ac, rs	microMIPSDSP	Extract Halfword Value Variable From Accumulator to GPR With Right Shift and Saturate
EXTR.W rt, ac, shift	microMIPSDSP	Extract Word Value With Right Shift From Accumulator to GPR
EXTR_R.W rt, ac, shift	microMIPSDSP	Extract Word Value With Right Shift From Accumulator to GPR
EXTR_RS.W rt, ac, shift	microMIPSDSP	Extract Word Value With Right Shift From Accumulator to GPR
EXTR_S.H rt, ac, shift	microMIPSDSP	Extract Halfword Value From Accumulator to GPR With Right Shift and Saturate
INS rt, rs	microMIPSDSP	Insert Bit Field Variable
LBUX rd, index(base)	microMIPSDSP	Load Unsigned Byte Indexed
LDX rd, index(base)	microMIPSDSP	Load Doubleword Indexed
LHX rd, index(base)	microMIPSDSP	Load Halfword Indexed
LWX rd, index(base)	microMIPSDSP	Load Word Indexed
MADD ac, rs, rt	microMIPS32 pre-Release 6, microMIPSDSP	Multiply Word and Add to Accumulator
MADDU ac, rs, rt	microMIPS32 pre-Release 6, microMIPSDSP	Multiply Unsigned Word and Add to Accumulator
MAQ_S.W.PHL ac, rs, rt	microMIPSDSP	Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_SA.W.PHL ac, rs, rt	microMIPSDSP	Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_S.W.PHR ac, rs, rt	microMIPSDSP	Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_SA.W.PHR ac, rs, rt	microMIPSDSP	Multiply with Accumulate Single Vector Fractional Halfword Element
MFHI rds, ac	microMIPS32 pre-Release 6, microMIPSDSP	Move from HI register
MFLO rdt, ac	microMIPS32 pre-Release 6, microMIPSDSP	Move from LO register
MODSUB rd, rs, rt	microMIPSDSP	Modular Subtraction on an Index Value
MSUB ac, rs, rt	microMIPS32 pre-Release 6, microMIPSDSP	Multiply Word and Subtract from Accumulator
MSUBU ac, rs, rt	microMIPS32 pre-Release 6, microMIPSDSP	Multiply Unsigned Word and Add to Accumulator
MTHI rs, ac	microMIPS32 pre-Release 6, microMIPSDSP	Move to HI register
MTHLIP rs, ac	microMIPSDSP	Copy LO to HI and a GPR to LO and Increment Pos by 32
MTLO rs, ac	microMIPS32 pre-Release 6, microMIPSDSP	Move to LO register
MULEQ_S.W.PHL rd, rs, rt	microMIPSDSP	Multiply Vector Fractional Left Halfwords to Expanded Width Products
MULEQ_S.W.PHR rd, rs, rt	microMIPSDSP	Multiply Vector Fractional Right Halfwords to Expanded Width Products
MULEU_S.PH.QBL rd, rs, rt	microMIPSDSP	Multiply Unsigned Vector Left Bytes by Halfwords to Halfword Products
MULEU_S.PH.QBR rd, rs, rt	microMIPSDSP	Multiply Unsigned Vector Right Bytes with halfwords to Half Word Products
MULQ_RS.PH rd, rs, rt	microMIPSDSP	Multiply Vector Fractional Halfwords to Fractional Halfword Products
MULQ_RS.W rd, rs, rt	microMIPSDSP-R2	Multiply Fractional Words to Same Size Product with Saturation and Rounding
MULQ_S.PH rd, rs, rt	microMIPSDSP-R2	Multiply Vector Fractional Half-Words to Same Size Products
MULQ_S.W rd, rs, rt	microMIPSDSP-R2	Multiply Fractional Words to Same Size Product with Saturation
MULSA.W.PH ac, rs, rt	microMIPSDSP-R2	Multiply and Subtract Vector Integer Halfword Elements and Accumulate
MULSAQ_S.W.PH ac, rs, rt	microMIPSDSP	Multiply And Subtract Vector Fractional Halfwords And Accumulate
MULT ac, rs, rt	microMIPS32 pre-Release 6, microMIPSDSP	Multiply Word
MULTU ac, rs, rt	microMIPS32 pre-Release 6, microMIPSDSP	Multiply Unsigned Word
MUL.PH rd, rs, rt	microMIPSDSP-R2	Multiply Vector Integer HalfWords to Same Size Products
MUL_S.PH rd, rs, rt	microMIPSDSP-R2	Multiply Vector Integer HalfWords to Same Size Products
PACKRL.PH rd, rs, rt	microMIPSDSP	Pack a Vector of Halfwords from Vector Halfword Sources
PICK.PH rd, rs, rt	microMIPSDSP	Pick a Vector of Halfword Values Based on Condition Code Bits
PICK.QB rd, rs, rt	microMIPSDSP	Pick a Vector of Byte Values Based on Condition Code Bits
PRECEQ.W.PHL rdt, rts	microMIPSDSP	Precision Expand Fractional Halfword to Fractional Word Value
PRECEQ.W.PHR rdt, rts	microMIPSDSP	Precision Expand Fractional Halfword to Fractional Word Value
PRECEQU.PH.QBLA rdt, rts	microMIPSDSP	Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBL rdt, rts	microMIPSDSP	Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBRA rdt, rts	microMIPSDSP	Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBR rdt, rts	microMIPSDSP	Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEU.PH.QBLA rdt, rts	microMIPSDSP	Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBL rdt, rts	microMIPSDSP	Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBRA rdt, rts	microMIPSDSP	Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBR rdt, rts	microMIPSDSP	Precision Expand two Unsigned Bytes to Unsigned Halfword Values
PRECR.QB.PH rd, rs, rt	microMIPSDSP-R2	Precision Reduce Four Integer Halfwords to Four Bytes
PRECRQ.PH.W rd, rs, rt	microMIPSDSP	Precision Reduce Fractional Words to Fractional Halfwords
PRECRQ.QB.PH rd, rs, rt	microMIPSDSP	Precision Reduce Four Fractional Halfwords to Four Bytes
PRECRQU_S.QB.PH rd, rs, rt	microMIPSDSP	Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation
PRECRQ_RS.PH.W rd, rs, rt	microMIPSDSP	Precision Reduce Fractional Words to Halfwords With Rounding and Saturation
PRECR_SRA.PH.W rt, rs, sa	microMIPSDSP-R2	Precision Reduce Two Integer Words to Halfwords after a Right Shift
PRECR_SRA_R.PH.W rt, rs, sa	microMIPSDSP-R2	Precision Reduce Two Integer Words to Halfwords after a Right Shift
PREPEND rt, rs, sa	microMIPSDSP-R2	Right Shift and Prepend Bits to the MSB
RADDU.W.QB rdt, rs	microMIPSDSP	Unsigned Reduction Add Vector Quad Bytes
RDDSP rdt, mask	microMIPSDSP	Read DSPControl Register Fields to a GPR
REPL.PH rd, immediate	microMIPSDSP	Replicate Immediate Integer into all Vector Element Positions
REPL.QB rdt, immediate	microMIPSDSP	Replicate Immediate Integer into all Vector Element Positions
REPLV.PH rdt, rts	microMIPSDSP	Replicate a Halfword into all Vector Element Positions
REPLV.QB rdt, rts	microMIPSDSP	Replicate Byte into all Vector Element Positions
SHILO ac, shift	microMIPSDSP	Shift an Accumulator Value Leaving the Result in the Same Accumulator
SHILOV ac, rs	microMIPSDSP	Variable Shift of Accumulator Value Leaving the Result in the Same Accumulator
SHLL.QB rdt, rts, sa	microMIPSDSP	Shift Left Logical Vector Quad Bytes
SHLLV.QB rd, rt, rs	microMIPSDSP	Shift Left Logical Variable Vector Quad Bytes
SHLLV.PH rd, rt, rs	microMIPSDSP	Shift Left Logical Variable Vector Pair Halfwords
SHLLV_S.PH rd, rt, rs	microMIPSDSP	Shift Left Logical Variable Vector Pair Halfwords
SHLLV_S.W rd, rt, rs	microMIPSDSP	Shift Left Logical Variable Vector Word
SHLL.PH rdt, rts, sa	microMIPSDSP	Shift Left Logical Vector Pair Halfwords
SHLL_S.PH rdt, rts, sa	microMIPSDSP	Shift Left Logical Vector Pair Halfwords
SHLL_S.W rdt, rts, sa	microMIPSDSP	Shift Left Logical Word with Saturation
SHRAV.PH rd, rt, rs	microMIPSDSP	Shift Right Arithmetic Variable Vector Pair Halfwords
SHRAV_R.PH rd, rt, rs	microMIPSDSP	Shift Right Arithmetic Variable Vector Pair Halfwords
SHRAV.QB rd, rt, rs	microMIPSDSP-R2	Shift Right Arithmetic Variable Vector of Four Bytes
SHRAV_R.QB rd, rt, rs	microMIPSDSP-R2	Shift Right Arithmetic Variable Vector of Four Bytes
SHRAV_R.W rd, rt, rs	microMIPSDSP	Shift Right Arithmetic Variable Word with Rounding
SHRA.PH rdt, rts, sa	microMIPSDSP	Shift Right Arithmetic Vector Pair Halfwords
SHRA_R.PH rdt, rts, sa	microMIPSDSP	Shift Right Arithmetic Vector Pair Halfwords
SHRA.QB rdt, rts, sa	microMIPSDSP-R2	Shift Right Arithmetic Vector of Four Bytes
SHRA_R.QB rdt, rts, sa	microMIPSDSP-R2	Shift Right Arithmetic Vector of Four Bytes
SHRA_R.W rdt, rts, sa	microMIPSDSP	Shift Right Arithmetic Word with Rounding
SHRL.PH rdt, rts, sa	microMIPSDSP-R2	Shift Right Logical Two Halfwords
SHRL.QB rdt, rts, sa	microMIPSDSP	Shift Right Logical Vector Quad Bytes
SHRLV.PH rd, rt, rs	microMIPSDSP-R2	Shift Variable Right Logical Pair of Halfwords
SHRLV.QB rd, rt, rs	microMIPSDSP	Shift Right Logical Variable Vector Quad Bytes
SUBQH.PH rd, rs, rt	microMIPSDSP-R2	Subtract Fractional Halfword Vectors And Shift Right to Halve Results
SUBQH_R.PH rd, rs, rt	microMIPSDSP-R2	Subtract Fractional Halfword Vectors And Shift Right to Halve Results
SUBQH.W rd, rs, rt	microMIPSDSP-R2	Subtract Fractional Words And Shift Right to Halve Results
SUBQH_R.W rd, rs, rt	microMIPSDSP-R2	Subtract Fractional Words And Shift Right to Halve Results
SUBQ.PH rd, rs, rt	microMIPSDSP	Subtract Fractional Halfword Vector
SUBQ_S.PH rd, rs, rt	microMIPSDSP	Subtract Fractional Halfword Vector
SUBQ_S.W rd, rs, rt	microMIPSDSP	Subtract Fractional Word
SUBUH.QB rd, rs, rt	microMIPSDSP-R2	Subtract Unsigned Bytes And Right Shift to Halve Results
SUBUH_R.QB rd, rs, rt	microMIPSDSP-R2	Subtract Unsigned Bytes And Right Shift to Halve Results
SUBU.PH rd, rs, rt	microMIPSDSP-R2	Subtract Unsigned Integer Halfwords
SUBU_S.PH rd, rs, rt	microMIPSDSP-R2	Subtract Unsigned Integer Halfwords
SUBU.QB rd, rs, rt	microMIPSDSP	Subtract Unsigned Quad Byte Vector
SUBU_S.QB rd, rs, rt	microMIPSDSP	Subtract Unsigned Quad Byte Vector
WRDSP rst, mask	microMIPSDSP	Write Fields to DSPControl Register from a GPR
MICROMIPS ASE-MCU ISA Reference		MD00838-2B-microMIPS32MUCON-AFP-01.03
ACLR bit, offset(base)	microMIPS, MCU ASE	Atomically Clear Bit within Byte
ASET bit, offset(base)	microMIPS, MCU ASE	Atomically Set Bit within Byte
IRET	microMIPS, MCU ASE	Interrupt Return with automated interrupt epilogue handling
MICROMIPS ASE-MT ISA Reference		MD00768-1C-microMIPS32MT-AFP-01.12
DMT rt	microMIPS, MIPS MT	Disable Multi-Threaded Execution
DVPE rt	microMIPS, MIPS MT	Disable Virtual Processor Execution
EVPE rt	microMIPS, MIPS MT	Enable Virtual Processor Execution
FORK rd, rs, rt	microMIPS, MIPS MT	Allocate and Schedule a New Thread
MFTR rs, rt, u, sel, h	microMIPS, MIPS MT	Move from Thread Context
MTTR rt, rs, u, sel, h	microMIPS, MIPS MT	Move to Thread Context
YIELD rs, rt	microMIPS, MIPS MT	Conditionally Deschedule or Deallocate the Current Thread
MICROMIPS ASE-VZ ISA Reference		MD00849-2B-VZmicroMIPS64-AFP-01.06
DMFGC0 rt, rs, sel	microMIPS64	Doubleword Move from Guest Coprocessor 0
DMTGC0 rt, rs, sel	microMIPS64	Doubleword Move to Guest Coprocessor 0
MFGC0 rt, rs, sel	microMIPS	Move from Guest Coprocessor 0
MFHGC0 rt, rs, sel	microMIPS Release 5	Move from High Guest Coprocessor 0
MTGC0 rt, rs, sel	microMIPS	Move to Guest Coprocessor 0
MTHGC0 rt, rs, sel	microMIPS Release 5	Move to High Guest Coprocessor 0
TLBGINV	microMIPS	Guest TLB Invalidate
TLBGINVF	microMIPS	Guest TLB Invalidate Flush
TLBGP	microMIPS	Probe Guest TLB for Matching Entry
TLBGR	microMIPS	Read Indexed Guest TLB Entry
TLBGWI	microMIPS	Write Indexed Guest TLB Entry
TLBGWR	microMIPS	Write Random Guest TLB Entry
TLBINV	microMIPS	TLB Invalidate
TLBINVF	microMIPS	TLB Invalidate Flush
TLBP	microMIPS	Probe TLB for Matching Entry
TLBR	microMIPS	Read Indexed TLB Entry
TLBWI	microMIPS	Write Indexed TLB Entry
TLBWR	microMIPS	Write Random TLB Entry