Encoding:

Format:

PRECEU.PH.QBL rdt, rts

Purpose:

Precision Expand Two Unsigned Bytes to Unsigned Halfword Values

Expand the precision of two unsigned byte values taken from the two left-most elements of a quad byte vector to create two unsigned halfword values.

Description:

rdt = sign_extend(expand_prec8u16(rts31..24) || expand_prec8u16(rts23..16))

The two left-most unsigned integer byte values from the four right-most byte elements in register rts are expanded to are then written to destination register rdt. The preci sion expansion is create two unsigned halfword values that achieved by pre-pending eight most-significant zeros to each original value to generate each 16 bit unsigned value.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = 08 || GPR[rts]31..24
tempA15..0 = 08 || GPR[rts]23..16
GPR[rdt]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled