Encoding:

Format:

MTHC0 rt, rs

MTHC0 rt, rs, sel

Purpose:

Move to High Coprocessor 0

To copy a word from a GPR to the upper 32 bits of a CP0 general register that has been extended by 32 bits.

Description:

 CPR[0, rs, sel][63:32] = GPR[rt]

The contents of general register rt are loaded into the Coprocessor 0 register specified by the combination of rs and

sel. Not all Coprocessor 0 registers support the sel field; the sel field must be set to zero.

When the Coprocessor 0 destination register specified is the EntryLo0 or EntryLo1 register, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. If RI/XI are not supported, the shift must still occur, but an MFHC0 instruction returns 0s for these two fields. The GPR is right-shifted by two to vacate the lower two bits, and two 0s are shifted in from the left.

The result is written to the upper 32 bits of MIPS64 EntryLo0 or EntryLo1, excluding RI/XI, which were placed in bits

63:62, that is, the write must appear atomic, as if both MTC0 and MTHC0 occurred together.

This feature supports MIPS32 backward compatibility of MIPS64 systems.

Restrictions:

Pre-Release 6: The results are UNDEFINED if Coprocessor 0 does not contain a register as specified by rs and sel, or if the register exists but is not extended by 32 bits, or the register is extended for XPA, but XPA is not supported or enabled.

Release 6: A write to the high part of a register that is reserved, not implemented for the current core, or that is not extended beyond 32 bits is ignored.

In a 64-bit processor, the MTHC0 instruction writes only the lower 32 bits of register rt into the upper 32 bits of the

Coprocessor register specified by rd and sel if the register is extended as defined by IsCoprocessorRegisterExtended(). The registers extended by Release 5 are those required for the XPA feature. Release 6 extends WatchHi to support MemoryMapID. These registers are identical to the same registers in the MIPS64 Architecture, other than

EntryLo0 and EntryLo1.

Operation:

if Config5MVH = 0 then SignalException(ReservedInstruction) endif
data = GPR[rt]
reg = rs 
if IsCoprocessorRegisterImplemented (0, reg, sel) and
   IsCoprocessorRegisterExtended (0, reg, sel) then
      if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
         if (Config3LPA = 1 and PageGrainELPA = 1) then // PABITS > 36
             CPR[0,reg,sel]31..30 = data1..0
             CPR[0,reg,sel]61:32 = data31..2 and ((1<<(PABITS-36))-1)
             CPR[0,reg,sel]63:62 = 02
      else
         CPR[0, reg, sel][63:32] = data31..0
      endif
else
   if ArchitectureRevision() >= 6 then
      // nop (no exceptions, coprocessor state not modified)
   else
      UNDEFINED
   endif
endif

Exceptions:

Coprocessor Unusable, Reserved Instruction