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TLBGINVF

Purpose:

Guest TLB Invalidate Flush

TLBGINVF invalidates a set of Guest TLB entries based on Index match. The virtual address and ASID are ignored in the match.

Implementation of the TLBGINVF instruction is optional. The implementation of this instruction is indicated by the

IE ield in Conig4. the EntryHIEHINV ield is required for

Implementation ofimplementation of TLBGINV and TLBGINVF instructions.

Support for TLBGINVF is recommend for implementations supporting VTLB/FTLB type TLB's.

Description:

On execution of the TLBGINVF instruction, all entries within range of guest Index are invalidated.

Behavior of the TLBGINVF instruction applies to all applicable guest TLB entries and is unaffected by the setting of the Wired register.

For JTLB-based MMU(Conig_MT=1):

TLBGINVF causes all entries in the guest JTLB to be invalidated. Index is unused.

For VTLB/FTLB-based MMU(Conig_MT=4):

TLBINVF with Index in guest VTLB range causes all entries in the guest VTLB to be invalidated.

TLBINVF with Index in guest FTLB range causes all entries in the single corresponding set in the guest FTLB to be invalidated.

If TLB invalidate walk is implemented in software (Conig4_IE=2), then software must do these steps:

1.one TLBGINV instruction is executed with an index in guest VTLB range (invalidates all matching guest

VTLB entries)

2.a TLBGINV instruction is executed for each guest FTLB set (invalidates all matching entries in guest FTLB set)

If TLB invalidate walk is implemented in hardware (Conig4_IE=3), then software must do these steps:

1.one TLBGINV instruction is executed (invalidates all matching entries in both guest FTLB & guest VTLB).

In this case, Index is unused.

In an implementation supporting GuestID (GuestCtl0_G1=1), matching of guest TLB entries includes comparison of the TLB entry GuestID with the Root GuestID control ield, GuestCtl1RID .

Note that the TLBGINVF instruction only invalidates guest virtual address translations in the guest TLB, invalidation of guest physical address translations requires execution of the equivalent TLBINVF instruction sequence in the root

TLB.

Restrictions:

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries visible as deined by the Conig4 register.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

For processors that do notinclude the standard TLB MMU, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

   if ( Guest.ConfigMT=1 or
      (Guest.ConfigMT=4 & Guest.Config4IE=2 & Index <= Guest.Config1MMU_SIZE-1))
      startnum = 0
      endnum = Guest.Config1MMU_SIZE-1
   endif
   // treating VTLB and FTLB as one array
   if (Guest.ConfigMT=4 & Guest.Config4IE=2 & Index > Guest.Config1MMU_SIZE-1)
      startnum = start of selected Guest FTLB set // implementation specific
      endnum = end of selected Guest FTLB set - 1 //implementation specifc
   endif
   if (Guest.ConfigMT=4 & Guest.Config4IE=3))
      startnum = 0
      endnum = Guest.Config1MMU_SIZE-1 +
      ((Guest.Config4FTLBWays + 2) * Guest.Config4FTLBSets)
   endif
   if IsCoprocessorEnabled(0) then
      for (i = startnum to endnum)
         if (GuestCtl0G1 = 1)
             if (Guest.TLB[i]GuestID = GuestCtl1RID)
                Guest.TLB[i]hardware_invalid = 1
             endif
         else
                Guest.TLB[i]hardware_invalid = 1
         endif
      endfor
   else
      SignalException(CoprocessorUnusable, 0)
   endif

Exceptions:

Coprocessor Unusable

Reserved Instruction