Encoding:

POOL32B

001000

reglist

base

SWM

1101

offset

6

5

5

4

12

Format: 

SWM32 {sregs, } {ra}, offset(base)

microMIPS

Store Word Multiple

Purpose:

Store Word Multiple

To store a sequence of consecutive words to memory

Description: 

 memory[GPR[base]+offset],...,memory[GPR[base]+offset+4*(fn(reglist))] = 
{GPR[16],{GPR[17],{GPR[18],{GPR[19],{GPR[20],{GPR[21],{GPR[22],{GPR[23],
{GPR[30]}}}}}}}}}{GPR[31]}

The least-significant 32-bit words of the GPRs defined by reglist are stored in memory at the location specified by the aligned effective address. The 12-bit signed offset is added to the contents of GPR base to form the effective address.

The following table shows the encoding of the reglist field.

reglist Encoding

(binary)

List of Registers Loaded

0 0 0 0 1

GPR[16]

0 0 0 1 0

GPR[16], GPR[17]

0 0 0 1 1

GPR[16], GPR[17], GPR[18]

0 0 1 0 0

GPR[16], GPR[17], GPR[18], GPR[19]

0 0 1 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20]

0 0 1 1 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21]

0 0 1 1 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22]

0 1 0 0 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23]

0 1 0 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23], GPR[30]

1 0 0 0 0

GPR[31]

1 0 0 0 1

GPR[16], GPR[31]

1 0 0 1 0

GPR[16], GPR[17], GPR[31]

1 0 0 1 1

GPR[16], GPR[17], GPR[18], GPR[31]

1 0 1 0 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[31]

1 0 1 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[31]

1 0 1 1 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[31]

1 0 1 1 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[31]

1 1 0 0 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23], GPR[31]

1 1 0 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23], GPR[30], GPR[31]

All other combinations

Reserved

The register numbers and the effective addresses are correlated using the order listed in the table, starting with the left-most register on the list and ending with the right-most register on the list. The effective address is incremented for each subsequent register on the list.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Restrictions:

Pre-Release 6: The effective address must be 32-bit aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation: 

vAddr = sign_extend(offset) + GPR[base]
for i=0 to fn(reglist)
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
   pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
   bytesel = vAddr2..0 xor (BigEndianCPU || 02)
   datadoubleword = GPR[gpr(reglist,i)]63-8*bytesel..0 || 08*bytesel
   StoreMemory (CCA, WORD, datadoubleword, pAddr, vAddr, DATA)
   vAddr = vAddr + 4
endfor
function fn(list)
   fn = (number of entries in list) - 1 
endfunction

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch