Encoding:

Format:

MFC0 rt, rs

MFC0 rt, rs, sel

Purpose:

Move from Coprocessor 0

To move the contents of a coprocessor 0 register to a general register.

Description:

 GPR[rt] = CPR[0,rs,sel]

The contents of the coprocessor 0 register specified by the combination of rs and sel are sign-extended and loaded into general register rt. Not all coprocessor 0 registers support the sel field. In those instances, the sel field must be zero.

When the coprocessor 0 register specified is the EntryLo0 or the EntryLo1 register, the RI/XI fields are moved to bits 31:30 of the destination register. This feature supports MIPS32 backward compatibility on a MIPS64 system.

Restrictions:

Pre-Release 6: The results are UNDEFINED if coprocessor 0 does not contain a register as specified by rs and sel.

Release 6: Reading a reserved register or a register that is not implemented for the current core configuration returns

0.

Operation:

reg = rs
if IsCoprocessorRegisterImplemented(0, reg, sel) then
   data = CPR[0, reg, sel]
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
      GPR[rt]29..0 = data29..0
      GPR[rt]31 = data63
      GPR[rt]30 = data62
      GPR[rt]63..32 = sign_extend(data63)
   else
      GPR[rt] = sign_extend(data)
   endif
else
   if ArchitectureRevision() >= 6 then
      GPR[rt] = 0
   else
      UNDEFINED
   endif
endif

Exceptions:

Coprocessor Unusable, Reserved Instruction