Encoding:

POOL32A

000000

rt

rs

rd

0

PRECRQU_S.QB.PH

0101101101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

PRECRQU_S.QB.PH

01111

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format:

PRECRQU_S.QB.PH rd, rs, rt

microMIPSDSP

Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation

Purpose:

Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation

Reduce the precision of four fractional halfwords with saturation to produce four unsigned byte values, with saturation.

Description:

rd = sign_extend(sat(reduce_prec(rs31..16)) || sat(reduce_prec(rs15..0)) || 
sat(reduce_prec(rt31..16)) || sat(reduce_prec(rt15..0)))

The four right-most Q15 fractional halfwords from registers rs and rt are used to create four unsigned byte values that are written to corresponding elements of destination register rd. The two right-most halfwords from the rs register and the two right-most halfwords from the rt register are used to create the four unsigned byte values.

Each unsigned byte value is created from the Q15 fractional halfword input value after first examining the sign and magnitude of the halfword. If the sign of the halfword value is positive and the value is greater than 0x7F80 hexadecimal, the result is clamped to the maximum positive 8-bit value (255 decimal, 0xFF hexadecimal). If the sign of the halfword value is negative, the result is clamped to the minimum positive 8-bit value (0 decimal, 0x00 hexadecimal).

Otherwise, the sign bit is discarded from the input and the result is taken from the eight most-significant bits that remain.

If clamping was needed to produce any of the unsigned output values, bit 22 of the DSPControl register is set to 1.

The sign of the left-most byte result is extended into the 32 most-significant bits of destination register rd.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempD7..0 = sat8ReducePrecision( GPR[rs]31..16 )
tempC7..0 = sat8ReducePrecision( GPR[rs]15..0 )
tempB7..0 = sat8ReducePrecision( GPR[rt]31..16 )
tempA7..0 = sat8ReducePrecision( GPR[rt]15..0 )
GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function sat8ReducePrecision( a15..0 )
   sign = a15
   mag14..0 = a14..0
   if ( sign = 0 ) then
      if ( mag14..0 > 0x7F80 ) then
         temp7..0 = 0xFF
          DSPControlouflag:22 = 1
      else
          temp7..0 = mag14..7
      endif
   else
      temp7..0 = 0x00
      DSPControlouflag:22 = 1
   endif
   return temp7..0
endfunction sat8ReducePrecision

Exceptions:

Reserved Instruction, DSP Disabled