Encoding:

Format:

ADDSC rd, rs, rt

Purpose:

Add Signed Word and Set Carry Bit

Add two signed 32-bit values and set the carry bit in the DSPControl register if the addition generates a carry-out bit.

Description:

DSPControl[c],rd = sign_extend(rs + rt)

The right-most 32-bit signed value in register rt is added to the right-most 32-bit signed value in register rs. The result is then sign-extended to 64 bits and written into register rd. The carry bit result out of the addition operation is written to bit 13 (the c field) of the DSPControl register.

This instruction does not modify the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

Operation:

temp32..0 = ( 0 || GPR[rs]31..0 ) + ( 0 || GPR[rt]31..0 )
DSPControlc:13 = temp32 
GPR[rd]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

Note that this is really two's complement (modulo) arithmetic on the two integer values, where the overflow is preserved in architectural state. The ADDWC instruction can be used to do an add using this carry bit. These instructions are provided in the MIPS32 ISA to support 64-bit addition and subtraction using two pairs of 3 2-bit GPRs to hold each 64-bit value. In the MIPS64 ISA, 64-bit addition and subtraction can be performed directly, without requiring the use of these instructions.