Encoding:

Format:

LWC1 ft, offset(base) 

Purpose:

Load Word to Floating Point

To load a word from memory to an FPR

Description:

 FPR[ft] = memory[GPR[base] + offset]

The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched and placed into the low word of FPR ft. If FPRs are 64 bits wide, bits 63..32 of FPR ft become UNPREDICTABLE. The

16-bit signed offset is added to the contents of GPR base to form the effective address.

Restrictions:

Pre-Release 6: An Address Error exception occurs if EffectiveAddress_1..0 != 0 (not word-aligned).

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
memdoubleword = LoadMemory(CCA, WORD, pAddr, vAddr, DATA)
bytesel = vAddr2..0 xor (BigEndianCPU || 02)
StoreFPR(ft, UNINTERPRETED_WORD, memdoubleword31+8*bytesel..8*bytesel)

Exceptions:

TLB Refill, TLB Invalid, Address Error, Reserved Instruction, Coprocessor Unusable, Watch