Encoding:

POOL32A

000000

sel

RDHWR

0111000000

Format:

RDHWR rt,rs,sel

microMIPS

Read Hardware Register

Purpose:

Read Hardware Register

To move the contents of a hardware register to a general purpose register (GPR) if that operation is enabled by privileged software.

The purpose of this instruction is to give user mode access to specific information that is otherwise only visible in kernel mode.

In Release 6, a sel field has been added to allow a register with multiple instances to be read selectively. Specifically it is used for PerfCtr.

Description:

 GPR[rt] = HWR[rs]; GPR[rt] = HWR[rs, sel]

If access is allowed to the specified hardware register, the contents of the register specified by rs (optionally sel in

Release 6) is sign-extended and loaded into general register rt. Access control for each register is selected by the bits in the coprocessor 0 HWREna register.

The available hardware registers, and the encoding of the rs field for each, are shown in Table 8.27.

Table 8.27 RDHWR Register Numbers

Register Number (rs Value)	Mnemonic	Description
0	CPUNum	Number of the CPU on which the program is currently running. This register provides read access to the coprocessor 0 EBaseCPUNum field.
1	SYNCI_Step	Address step size to be used with the SYNCI instruction, or zero if no caches need be synchronized. See that instruction's description for the use of this value.
2	CC	High-resolution cycle counter. This register provides read access to the coprocessor 0 Count Register.
3	CCRes	Resolution of the CC register. This value denotes the number of cycles between update of the register. For example: CCRes ValueMeaning 1CC register increments every CPU cycle 2CC register increments every second CPU cycle 3CC register increments every third CPU cycle etc.
4	PerfCtr	Performance Counter Pair. Even sel selects the Control register, while odd sel selects the Counter register in the pair. The value of sel corresponds to the value of sel used by MFC0 to read the CP0 register.
5	XNP	Indicates support for the Release 6 Paired LL/SC family of instructions. If set to 1, the LL/SC family of instructions is not present, otherwise, it is present in the implementation. In absence of hardware support for double-width or extended atomics, user software may emulate the instruction's behavior through other means. See Config5XNP.
6-28		These registers numbers are reserved for future architecture use. Access results in a Reserved Instruction Exception.
29	ULR	User Local Register. This register provides read access to the coprocessor 0 UserLocal register, if it is implemented. In some operating environments, the UserLocal register is a pointer to a thread-specific storage block.
30-31		These register numbers are reserved for implementation-dependent use. If they are not implemented, access results in a Reserved Instruction Exception.

Restrictions:

In implementations of Release 1 of the Architecture, this instruction resulted in a Reserved Instruction Exception.

Access to the specified hardware register is enabled if Coprocessor 0 is enabled, or if the corresponding bit is set in the HWREna register. If access is not allowed or the register is not implemented, a Reserved Instruction Exception is signaled.

In Release 6, when the 3-bit sel is undefined for use with a specific register number, then a Reserved Instruction

Exception is signaled.

Availability and Compatibility:

This instructions has been recoded for Release 6. The instruction supports a sel field in Release 6.

Operation:

   if ((rs!=4) and (sel==0))
case rs
      0: temp = sign_extend(EBase_CPUNum)
   1: temp = sign_extend(SYNCI_StepSize())
   2: temp = sign_extend(Count)
   3: temp = sign_extend(CountResolution())
      if (>=2) // #5 - Release 6
         5: temp = sign_extend(0x00000001 && Config5_XNP)//zero-extend really
      endif
   29: temp = sign_extend_if_32bit_op(UserLocal)
          endif 
   30: temp = sign_extend_if_32bit_op(Implementation-Dependent-Value)
   31: temp = sign_extend_if_32bit_op(Implementation-Dependent-Value)
   otherwise: SignalException(ReservedInstruction)
endcase
   elseif ((rs==4) and (>=2) and (sel==defined)// #4 - Release 6
      temp = sign_extend_if_32bit_op(PerfCtr[sel])
   else 
   endif
GPR[rt] = temp
function sign_extend_if_32bit_op(value)
   if (width(value) = 64) and Are64BitOperationsEnabled() then
      sign_extend_if_32bit_op = value
   else
      sign_extend_if_32bit_op = sign_extend(value)
   endif
end sign_extend_if_32bit_op

Exceptions:

Reserved Instruction

For a register that does not require sel, the compiler must support an assembly syntax without sel that is 'RDHWR rt, rs'. Another valid syntax is for sel to be 0 to map to pre-Release 6 register numbers which do not require use of sel that is, 'RDHWR rt, rs, 0'.