Encoding:

Format:

SHLLV.QB rd, rt, rs

Purpose:

Shift Left Logical Variable Vector Quad Bytes

Element-wise left shift of four independent bytes in a vector data type by a variable number of bits.

Description:

rd = sign_extend((rt31..24 << rs2..0) || (rt23..16 << rs2..0) || (rt15..8 << rs2..0) || (rt7..0 << rs2..0))

The four right-most byte values in register rt are each independently shifted left by sa bits, inserting zeros into the least-significant bit positions emptied by the shift. The four independent results are then written to the corresponding byte elements of destination register rd.

The sign of the left-most byte result is extended into the 32 most-significant bits of the destination register.

The three least-significant bits of rs provide the shift value, interpreted as a three-bit unsigned integer; the remaining bits of rs are ignored.

This instruction writes a 1 to bit 22 in the DSPControl register in the ouflag field if any of the left shift operations results in an overflow.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempD7..0 = shift8Left( GPR[rt]31..24, GPR[rs]2..0 )
tempC7..0 = shift8Left( GPR[rt]23..16, GPR[rs]2..0 )
tempB7..0 = shift8Left( GPR[rt]15..8, GPR[rs]2..0 )
tempA7..0 = shift8Left( GPR[rt]7..0, GPR[rs]2..0 )
GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0

Exceptions:

Reserved Instruction, DSP Disabled