POOL32F 010101 |
ft |
fs |
0 |
fmt |
CVT.L 00000100 |
POOL32FXf 111011 |
6 |
5 |
5 |
1 |
1 |
8 |
6 |
CVT.L.fmt |
Floating Point Convert to Long Fixed Point | |
CVT.L.S ft, fs |
MIPS64, microMIPS |
Floating Point Convert to Long Fixed Point |
CVT.L.D ft, fs |
MIPS64, microMIPS |
Floating Point Convert to Long Fixed Point |
Floating Point Convert to Long Fixed Point
To convert an FP value to a 64-bit fixed point.
FPR[ft] = convert_and_round(FPR[fs])
Convert the value in format fmt in FPR fs to long fixed point format and round according to the current rounding mode in FCSR. The result is placed in FPR ft.
When the source value is Infinity, NaN, or rounds to an integer outside the range -263 to 263-1, the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise, a default result is written to ft. On cores with FCSRNAN2008=0, the default result is
263-1. On cores with FCSRNAN2008=1, the default result is:
0 when the input value is NaN
263-1 when the input value is +inf or rounds to a number larger than 263-1
-263-1 when the input value is - or rounds to a number smaller than -263-1
The fields fs and ft must specify valid FPRs, fs for type fmt and fd for long fixed point. If the fields are not valid, the result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
StoreFPR (ft, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))
Coprocessor Unusable, Reserved Instruction
Invalid Operation, Unimplemented Operation, Inexact,