Encoding:

Format:

ERET 

Purpose:

Exception Return

To return from interrupt, exception, or error trap.

Description:

ERET clears execution and instruction hazards, conditionally restores SRSCtl_CSS from SRSCtl_PSS in a Release 2 implementation, and returns to the interrupted instruction at the completion of interrupt, exception, or error processing. ERET does not execute the next instruction (that is, it has no delay slot).

Restrictions:

Pre-Release 6: The operation of the processor is UNDEFINED if an ERET is executed in the delay slot of a branch or jump instruction. In Release 6, in the absence of delay/forbidden slots, this restriction does not apply.

An ERET placed between an LL and SC instruction will always cause the SC to fail.

ERET implements a software barrier that resolves all execution and instruction hazards created by Coprocessor 0 state changes (for Release 2 implementations, refer to the SYNCI instruction for additional information on resolving instruction hazards created by writing the instruction stream). The effects of this barrier are seen starting with the instruction fetch and decode of the instruction at the PC to which the ERET returns.

In a Release 2 implementation, ERET does not restore SRSCtl_CSS from SRSCtl_PSS if Status_BEV = 1, or if Status_ERL

= 1 because any exception that sets Status_ERL to 1 (Reset, Soft Reset, NMI, or cache error) does not save SRSCtl_CSS in SRSCtlPSS. If software sets StatusERL to 1, it must be aware of the operation of an ERET that may be subsequently executed.

Operation:

if StatusERL = 1 then
   temp = ErrorEPC
   StatusERL = 0
else
   temp = EPC
   StatusEXL = 0
   if (ArchitectureRevision() >= 2) and (SRSCtlHSS > 0) and (StatusBEV = 0) then
      SRSCtlCSS = SRSCtlPSS
   endif
endif
if IsMIPS16Implemented() | (Config3ISA > 0) then
   PC = temp63..1 || 0
   ISAMode = temp0
else
   PC = temp
endif
LLbit = 0
ClearHazards()

Exceptions:

Coprocessor Unusable Exception