Encoding:

Format:

MADDF.fmt MSUBF.fmt 

MADDF.S fd, fs, ft

MADDF.D fd, fs, ft

MSUBF.S fd, fs, ft

MSUBF.D fd, fs, ft

Purpose:

Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract

MADDF.fmt: To perform a fused multiply-add of FP values.

MSUBF.fmt: To perform a fused multiply-subtract of FP values.

Description:

MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] <= FPR[ft])
MSUBF.fmt: FPR[fd] = FPR[fd] - (FPR[fs] <= FPR[ft])

The value in FPR fs is multiplied by the value in FPR ft to produce an intermediate product. The intermediate product is calculated to infinite precision. The product is added to the value in FPR fd. The result sum is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt.

(For MSUBF fmt, the product is subtracted from the value in FPR fd.)

Cause bits are ORed into the Flag bits if no exception is taken.

Restrictions:

None

Availability and Compatibility:

MADDF.fmt and MSUBF.fmt are required in Release 6.

MADDF.fmt and MSUBF.fmt are not available in architectures pre-Release 6.

The fused multiply add instructions, MADDF.fmt and MSUBF fmt, replace pre-Release 6 instructions such as

MADD fmt, MSUB.fmt, NMADD.fmt, and NMSUB.fmt. The replaced instructions were unfused multiply-add, with an intermediate rounding.

Release 6 MSUBF fmt, fd=fd-fs<=ft, corresponds more closely to pre-Release 6 NMADD fmt, fd=fr-fs<=ft, than to pre-Release 6 MSUB.fmt, fd=fs<=ft-fr.

FPU scalar MADDF fmt corresponds to MSA vector MADD.df.

FPU scalar MSUBF fmt corresponds to MSA vector MSUB.df.

Operation:

if not IsCoprocessorEnabled(1) 
   then SignalException(CoprocessorUnusable, 1) endif
if not IsFloatingPointImplemented(fmt)) 
   then SignalException(ReservedInstruction) endif
vfr = ValueFPR(fr, fmt)
vfs = ValueFPR(fs, fmt)
vfd = ValueFPR(fd, fmt)
MADDF.fmt: vinf = vfd +inf (vfs *inf vft)
MSUBF.fmt: vinf = vfd -inf (vfs *inf vft)
StoreFPR(fd, fmt, vinf)

Special Considerations:

The fused multiply-add computation is performed in infinite precision, and signals Inexact, Overflow, or Underflow if and only if the final result differs from the infinite precision result in the appropriate manner.

Like most FPU computational instructions, if the flush-subnormals-to-zero mode, FCSR.FS=1, then subnormals are flushed before beginning the fused-multiply-add computation, and Inexact may be signaled.

I.e. Inexact may be signaled both by input flushing and/or by the fused-multiply-add: the conditions or ORed.

Exceptions:

Coprocessor Unusable, Reserved Instruction

Floating Point Exceptions:

Inexact, Unimplemented Operation, Invalid Operation, Overflow, Underflow