POOL32A 000000 |
rt |
rs |
rd |
0 |
PICK.PH 1000101101 |
6 |
5 |
5 |
5 |
1 |
10 |
SPECIAL3 011111 |
rs |
rt |
rd |
PICK.PH 01011 |
CMPU.EQ.QB 010001 |
6 |
5 |
5 |
5 |
5 |
6 |
PICK.PH rd, rs, rt |
microMIPSDSP |
Pick a Vector of Halfword Values Based on Condition Code Bits |
Pick a Vector of Halfword Values Based on Condition Code Bits
Select two halfword elements from e ither of two source registers based on condition code bits, writing the selected elements to the destination register.
rd = sign_extend(pick(cc25,rs31..16,rt31..16) || pick(cc24,rs15..0,rt15..0))
The two right-most condition code bits in the DSPControl register are used to select halfword values from the corresponding element of either source register rs or source register rt. If the value of the corresponding condition code bit is 1, then the halfword value is selected from register rs; otherwise, it is selected from rt. The selected halfwords are written to the destination register rd.
The sign of the left-most halfword result is sign-extended into the 32 most-significant bits of the destination register.
No data-dependent exceptions are possible.
The operands must be in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
tempB15..0 = ( DSPControlccond:25 = 1 ? GPR[rs]31..16 : GPR[rt]31..16 ) tempA15..0 = ( DSPControlccond:24 = 1 ? GPR[rs]15..0 : GPR[rt]15..0 ) GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
Reserved Instruction, DSP Disabled