Encoding:

Format:

LWP rd, offset(base)

Purpose:

Load Word Pair

To load two consecutive words from memory

Description:

 GPR[rd], GPR[rd+1] = memory[GPR[base] + offset]

The contents of the two consecutive 32-bit words at the memory location specified by the 32-bit aligned effective address are fetched, sign-extended to the GPR register length if necessary, and placed in GPR rd and (rd+1). The

12-bit signed offset is added to the contents of GPR base to form the effective address.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Restrictions:

The behavior of the instructions is UNPREDICTABLE if rd equals r31.

The behavior of the instruction is UNPREDICTABLE, if base and rd are the same. Reason for this is to allow restartability of the operation if an interrupt or exception has aborted the operation in the middle.

Pre-Release 6: The effective address must be 32-bit aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
memdoubleword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
byte = vAddr2..0 xor (BigEndianCPU || 02)
GPR[rd] = sign_extend(memdoubleword31+8*byte..8*byte)
vAddr = sign_extend(offset) + GPR[base] + 4
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
memdoubleword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
byte = vAddr2..0 xor (BigEndianCPU || 02)
GPR[rd+1]= sign_extend(memdoubleword31+8*byte..8*byte)

Exceptions:

TLB Refill, TLB Invalid, Bus Error, Address Error, Watch