Encoding:

Format:

LDP rd, offset(base)

Purpose:

Load Doubleword Pair

To load two consecutive doublewords from memory

Description:

 GPR[rd], GPR[rd+1] = memory[GPR[base] + offset]

The contents of the two consecutive 64-bit words at the memory location specified by the aligned effective address are fetched and placed in GPR rd and (rd+1). The 12-bit signed offset is added to the contents of GPR base to form the effective address.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Restrictions:

The behavior of the instructions is UNDEFINED if rd equals $31.

The behavior of the instruction is UNDEFINED, if base and rd are the same. Reason for this is to allow restartability of the operation if an interrupt or exception has aborted the operation in the middle.

Pre-Release 6: The effective address must be naturally aligned. If any of the 3 least-significant bits of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation:

if (Are64bitOperationsEnabled() then
   vAddr = sign_extend(offset) + GPR[base]
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)=
   memdoubleword = LoadMemory (CCA, DOUBLEWORD, pAddr, vAddr, DATA)=
   GPR[rd] = memdoubleword
   vAddr = sign_extend(offset) + GPR[base] + 8
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)=
   memdoubleword = LoadMemory (CCA, DOUBLEWORD, pAddr, vAddr, DATA)=
   GPR[rd+1]= memdoubleword)
else
   SignalException(ReservedInstruction)
endif

Exceptions:

TLB Refill, TLB Invalid, Bus Error, Address Error, Reserved Instruction, Watch

Programming Notes:

This instruction may execute for a variable number of cycles and performs two loads from memory. A full restart of the sequence of operations will be performed on return from any exception taken during execution.