Encoding:

Format:

MTC0 rt, rs

MTC0 rt, rs, sel

Purpose:

Move to Coprocessor 0

To move the contents of a general register to a coprocessor 0 register.

Description:

 CPR[0, rs, sel] = GPR[rt]

The contents of general register rt are loaded into the coprocessor 0 register specified by the combination of rs and

sel. Not all coprocessor 0 registers support the sel field. In those instances, the sel field must be set to zero.

When the CP0 destination register specified is the EntryLo0 or the EntryLo1 register, bits 31:30 appear in the RI/XI fields of the destination register. This feature supports MIPS32 backward compatibility on a MIPS64 implementation.

Restrictions:

Pre-Release 6: The results are UNDEFINED if coprocessor 0 does not contain a register as specified by rs and sel.

Release 6: Writes to a register that is reserved or not defined for the current core configuration are ignored.

Operation:

data = GPR[rt]
reg = rs
if IsCoprocessorRegisterImplemented (0, reg, sel) then
   if (reg,sel = EntryLo1 or EntryLo0) then
      CPR[0,reg,sel]29..0 = data29..0
      CPR[0,reg,sel]63 = data31
      CPR[0,reg,sel]62 = data30
      CPR[0,reg,sel]61:30 = 032
   elseif (Width(CPR[0,reg,sel]) = 64) then
      CPR[0,reg,sel] = data
   else
      CPR[0,reg,sel] = data31..0
   endif
else
   if ArchitectureRevision() >= 6 then
   // nop (no exceptions, coprocessor state not modified)
   else
      UNDEFINED
   endif
endif

Exceptions:

Coprocessor Unusable, Reserved Instruction