Encoding:

Format:

TLBINV 

Purpose:

TLB Invalidate

TLBINV invalidates a set of TLB entries based on ASID and Index match. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified.

Implementation of the TLBINV instruction is optional. The implementation of this instruction is indicated by the IE field in Config4.

Support for TLBINV is recommend for implementations supporting VTLB/FTLB type of MMU.

Implementation of EntryHI_EHINV field is required for implementation of TLBINV instruction.

Description:

On execution of the TLBINV instruction, the set of TLB entries with matching ASID are marked invalid, excluding those TLB entries which have their G bit set to 1.

The EntryHI_ASID field has to be set to the appropriate ASID value before executing the TLBINV instruction.

Behavior of the TLBINV instruction applies to all applicable TLB entries and is unaffected by the setting of the Wired register.

• For JTLB-based MMU (Config_MT=1):

All matching entries in the JTLB are invalidated. The Index register is unused.

• For VTLB/FTLB -based MMU (Config_MT=4):

If TLB invalidate walk is implemented in software (Config4_IE=2), then software must do these steps to flush the entire MMU:

1.one TLBINV instruction is executed with an index in VTLB range (invalidates all matching VTLB entries)

2.a TLBINV instruction is executed for each FTLB set (invalidates all matching entries in FTLB set)

If TLB invalidate walk is implemented in hardware (Config4_IE=3), then software must do these steps to flush the entire MMU:

1.one TLBINV instruction is executed (invalidates all matching entries in both FTLB & VTLB). In this case,

Index is unused.

Restrictions:

When Config4_MT = 4 and Config4_IE = 2, the operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of available TLB entries.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Availability and Compatibility:

Implementation of the TLBINV instruction is optional. The implementation of this instruction is indicated by the IE field in Config4.

Implementation of EntryHI_EHINV field is required for implementation of TLBINV instruction.

Pre-Release 6, support for TLBINV is recommended for implementations supporting VTLB/FTLB type of MMU.

Release 6 (and subsequent releases) support for TLBINV is required for implementations supporting VTLB/FTLB type of MMU.

Release 6: On processors that include a Block Address Translation (BAT) or Fixed Mapping (FM) MMU (Config_MT =

2 or 3), the operation of this instruction causes a Reserved Instruction exception (RI).

Operation:

   if ( ConfigMT=1 or (ConfigMT=4 & Config4IE=2 & Index < VTLBsize() )) 
      startnum = 0
      endnum = VTLBsize() - 1
   endif
   // treating VTLB and FTLB as one array 
   if (ConfigMT=4 & Config4IE=2 & Index >= VTLBsize(); ) 
      startnum = start of selected FTLB set // implementation specific
      endnum = end of selected FTLB set - 1 //implementation specifc
   endif
   if (ConfigMT=4 & Config4IE=3)) 
      startnum = 0
      endnum = VTLBsize() + FTLBsize() - 1;
   endif
   for (i = startnum to endnum) 
      if (TLB[i]ASID = EntryHiASID & TLB[i]G = 0) 
         TLB[i]VPN2_invalid = 1
      endif
   endfor
function VTLBsize 
   SizeExt = ArchRev() >= 6          ?  Config4VTLBSizeExt
         : Config4MMUExtDef == 3     ?  Config4VTLBSizeExt
         : Config4MMUExtDef == 1     ?  Config4MMUSizeExt
         :               0
         ;
    return 1 + ( (SizeExt << 6) | Config1.MMUSize );
endfunction
function FTLBsize 
   if ( Config1MT == 4 ) then
      return ( Config4FTLBWays + 2 ) * ( 1 << C0_Config4FTLBSets );
   else 
      return 0;
   endif
endfunction

Exceptions:

Coprocessor Unusable,