Encoding:

Format:

WAIT 

Purpose:

Enter Standby Mode

Wait for Event

Description:

The WAIT instruction performs an implementation-dependent operation, involving a lower power mode. Software may use the code bits of the instruction to communicate additional information to the processor. The processor may use this information as control for the lower power mode. A value of zero for code bits is the default and must be valid in all implementations.

The WAIT instruction is implemented by stalling the pipeline at the completion of the instruction and entering a lower power mode. The pipeline is restarted when an external event, such as an interrupt or external request occurs, and execution continues with the instruction following the WAIT instruction. It is implementation-dependent whether the pipeline restarts when a non-enabled interrupt is requested. In this case, software must poll for the cause of the restart. The assertion of any reset or NMI must restart the pipeline and the corresponding exception must be taken.

If the pipeline restarts as the result of an enabled interrupt, that interrupt is taken between the WAIT instruction and the following instruction (EPC for the interrupt points at the instruction following the WAIT instruction).

In Release 6, the behavior of WAIT has been modified to make it a requirement that a processor that has disabled operation as a result of executing a WAIT will resume operation on arrival of an interrupt even if interrupts are not enabled.

In Release 6, the encoding of WAIT with bits 25:16 of the opcode set to 0 will never disable CP0 Count on an active

WAIT instruction. In particular, this modification has been added to architecturally specify that CP0 Count is not disabled on execution of WAIT with default code of 0. Prior to Release 6, whether Count is disabled was implementation-dependent. In the future, other encodings of WAIT may be defined which specify other forms of power-saving or stand-by modes. If not implemented, then such unimplemented encodings must default to WAIT 0.

Restrictions:

Pre-Release 6: The operation of the processor is UNDEFINED if a WAIT instruction is executed in the delay slot of a branch or jump instruction.

Release 6: Implementations are required to signal a Reserved Instruction exception if WAIT is encountered in the delay slot or forbidden slot of a branch or jump instruction.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

Pre-Release 6:

I: Enter implementation dependent lower power mode
I+1:/* Potential interrupt taken here */

Release 6:

I: if IsCoprocessorEnabled(0) then
      while ( !interrupt_pending_and_not_masked_out() && 
             !implementation_dependent_wake_event() ) 
         < enter or remain in low power mode or stand-by mode>
   else
      SignalException(CoprocessorUnusable, 0)
   endif
 
I+1:  if ( interrupt_pending() && interrupts_enabled() ) then
         EPC = PC + 4
         < process interrupt; execute ERET eventually >
      else 
             // unblock on non-enabled interrupt or imp dep wake event.
             PC = PC + 4
             < continue execution at instruction after wait >
      endif
 
 function interrupt_pending_and_not_masked_out 
     return (Config3VEIC && IntCtlVS && CauseIV && !StatusBEV)
             ? CauseRIPL > StatusIPL : CauseIP & StatusIM;
 endfunction
 
 function interrupts_enabled 
     return StatusIE && !StatusEXL && !StatusERL && !DebugDM;
  endfunction
 
function implementation_dependent_wake_event
    <return true if implementation dependent waking-up event occurs>
 endfunction

Exceptions:

Coprocessor Unusable Exception