Encoding:

Format:

ERETNC 

Purpose:

Exception Return No Clear

To return from interrupt, exception, or error trap without clearing the LLbit.

Description:

ERETNC clears execution and instruction hazards, conditionally restores SRSCtl_CSS from SRSCtl_PSS when implemented, and returns to the interrupted instruction at the completion of interrupt, exception, or error processing.

ERETNC does not execute the next instruction (i.e., it has no delay slot).

ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail.

An ERET must continue to be used by default in interrupt and exception processing handlers. The handler may have accessed a synchronizable block of memory common to code that is atomically accessing the memory, and where the code caused the exception or was interrupted. Similarly, a process context-swap must also continue to use an ERET in order to avoid a possible false success on execution of SC in the restored context.

Multiprocessor systems with non-coherent cores (i.e., without hardware coherence snooping) should also continue to use ERET, because it is the responsibility of software to maintain data coherence in the system.

An ERETNC is useful in cases where interrupt/exception handlers and kernel code involved in a process contextswap can guarantee no interference in accessing synchronizable memory across different contexts. ERETNC can also be used in an OS-level debugger to single-step through code for debug purposes, avoiding the false clearing of the

LLbit and thus failure of an LL and SC sequence in single-stepped code.

Software can detect the presence of ERETNC by reading Config5_LLB.

Restrictions:

ERETNC implements a software barrier that resolves all execution and instruction hazards created by Coprocessor 0 state changes. (For Release 2 implementations, refer to the SYNCI instruction for additional information on resolving instruction hazards created by writing the instruction stream.) The effects of this barrier are seen starting with the instruction fetch and decode of the instruction in the PC to which the ERETNC returns.

Operation:

if StatusERL = 1 then
   temp = ErrorEPC
   StatusERL = 0
else
   temp = EPC
   StatusEXL = 0
   if (ArchitectureRevision() >= 2) and (SRSCtlHSS > 0) and (StatusBEV = 0) then
      SRSCtlCSS = SRSCtlPSS
   endif
endif
if IsMIPS16Implemented() | (Config3ISA > 0) then
   PC = temp63..1 || 0
   ISAMode = temp0
else
   PC = temp
endif
ClearHazards()

Exceptions:

Coprocessor Unusable Exception