Encoding:

Format:

TLBR 

Purpose:

Read Indexed TLB Entry

To read an entry from the TLB.

Description:

The EntryHi, EntryLo0, EntryLo1, and PageMask registers are loaded with the contents of the TLB entry pointed to by the Index register.

• In Release 1 of the Architecture, it is implementation dependent whether multiple TLB matches are detected on a

TLBR. However, implementations are strongly encouraged to report multiple TLB matches only on a TLB write.

• In Release 2 of the Architecture, multiple TLB matches may only be reported on a TLB write.

• In Release 3 of the Architecture, multiple TLB matches may be detected on a TLBR.

In an implementation supporting TLB entry invalidation (Config4_IE >= 1), reading an invalidated TLB entry causes

EntryLo0 and EntryLo1 to be set to 0, EntryHi_EHINV to be set to 1, all other EntryHi bits to be set to 0, and

PageMask to be set to a value representing the minimum supported page size..

The value written to the EntryHi, EntryLo0, and EntryLo1 registers may be different from the original written value to the TLB via these registers in that:

The value returned in the VPN2 field of the EntryHi register may have those bits set to zero corresponding to the

• one bits in the Mask field of the TLB entry (the least-significant bit of VPN2 corresponds to the least-significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.

The value returned in the PFN field of the EntryLo0 and EntryLo1 registers may have those bits set to zero cor-

• responding to the one bits in the Mask field of the TLB entry (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.

The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the

• TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written.

Restrictions:

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled. Release 6: Processors that include a Block Address Translation (BAT) or Fixed Mapping (FM) MMU (ConfigMT = 2 or 3), the operation of this instruction causes a Reserved Instruction exception (RI).

Operation:

i = Index
if i > (TLBEntries - 1) then
   UNDEFINED
endif
if ( (Config4IE >= 1) and TLB[i]VPN2_invalid = 1) then
   PagemaskMask = 0 // or value representing minimum page size
   EntryHi = 0
   EntryLo1 = 0
   EntryLo0 = 0
   EntryHiEHINV = 1
else
   PageMaskMask = TLB[i]Mask
   EntryHi = TLB[i]R || 0Fill ||
             (TLB[i]VPN2 and not TLB[i]Mask) || # Masking implem dependent
             05 || TLB[i]ASID
   EntryLo1 = 0Fill ||
             (TLB[i]PFN1 and not TLB[i]Mask) || # Masking mplem dependent
             TLB[i]C1 || TLB[i]D1 || TLB[i]V1 || TLB[i]G
   EntryLo0 = 0Fill ||
          (TLB[i]PFN0 and not TLB[i]Mask) || # Masking mplem dependent
          TLB[i]C0 || TLB[i]D0 || TLB[i]V0 || TLB[i]G
endif

Exceptions:

Coprocessor Unusable, Machine Check