Encoding:

Format:

MFHC1 rt, fs

Purpose:

Move Word From High Half of Floating Point Register

To copy a word from the high half of an FPU (CP1) general register to a GPR.

Description:

 GPR[rt] = sign_extend(FPR[fs]63..32)

The contents of the high word of FPR fs are sign-extended and loaded into general register rt. This instruction is primarily intended to support 64-bit floating point units on a 32-bit CPU, but the semantics of the instruction are defined for all cases.

Restrictions:

In implementations prior to Release 2 of the architecture, this instruction resulted in a Reserved Instruction exception.

The results are UNPREDICTABLE if Status_FR = 0 and fs is odd.

Operation:

data = ValueFPR(fs, UNINTERPRETED_DOUBLEWORD)63..32
GPR[rt] = sign_extend(data)

Exceptions:

Coprocessor Unusable, Reserved Instruction