Encoding:

POOL32A

000000

rt

rs

rd

0

PRECRQ_RS.PH.W

0100101101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

PRECRQ_RS.PH.W

10101

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format:

PRECRQ_RS.PH.W rd, rs, rt

microMIPSDSP

Precision Reduce Fractional Words to Halfwords With Rounding and Saturation

Purpose:

Precision Reduce Fractional Words to Halfwords With Rounding and Saturation

Reduce the precision of two fractional words to produce two fractional halfword values, with rounding and saturation.

Description:

rd = sign_extend(truncQ15SatRound(rs31..0) || truncQ15SatRound(rt31..0))

The two right-most Q31 fractional wo rd values in each of registers rs and rt are used to create two Q15 fractional halfword values that are written to the two right-most halfword elements in destination register rd. The right-most fractional word from the rs register is used to create the left-most Q15 fractional halfword result in rd, and the rightmost fractional word from the rt register is used to create the right-most halfword value.

Each input Q31 fractional value is rounded and saturated before being truncated to create the Q15 fractional halfword result. First, the value 0x00008000 is added to the input Q31 value to round even, creating an interim rounded result.

If this addition causes overflow, the interim rounded result is saturated to the maximum Q31 value (0x7FFFFFFF hexadecimal). Then, the 16 least-significant bits of the interim rounded and saturated result are discarded and the 16 most-significant bits are written to the destination register in the appropriate position.

The sign of the left-most halfword result is sign-extended into the 32 most-significant bits of the destination register.

If either of the rounding operations results in overflow and saturation, a 1 is written to bit 22 in the DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = trunc16Sat16Round( GPR[rs]31..0 )
tempA15..0 = trunc16Sat16Round( GPR[rt]31..0 )
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
function trunc16Sat16Round( a31..0 )
   temp32..0 = ( a31 || a31..0 ) + 0x00008000
   if ( temp32 != temp31 ) then
      temp32..0 = 0 || 0x7FFFFFFF
      DSPControlouflag:22 = 1
   endif
   return temp31..16
endfunction trunc16Sat16Round

Exceptions:

Reserved Instruction, DSP Disabled