Encoding:

POOL32A

000000

rt

rs

rd

0

SHRLV.QB

1101010101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

SHRLV.QB

00011

SHLL.QB

010011

6

5

5

5

5

6

Format: 

SHRLV.QB rd, rt, rs

microMIPSDSP

Shift Right Logical Variable Vector Quad Bytes

Purpose:

Shift Right Logical Variable Vector Quad Bytes

Element-wise logical right shift of four independent bytes in a vector data type by a variable number of bits.

Description: 

rd = sign_extend((rt31..24 >> rs2..0) || (rt23..16 >> rs2..0) || (rt15..8 >> rs2..0) || (rt7..0 >> rs2..0))

The four right-most byte values in register rt are each independently shifted right, inserting zeros into the most-significant bit positions emptied by the shift. The four independent results are then written to the corresponding byte elements of destination register rd.

The sign of the left-most result is extended into the 32 most-significant bits of the destination register.

The three least-significant bits of rs provide the shift value, interpreted as an unsigned integer; the remaining bits of

rs are ignored.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

tempD7..0 = shift8Right( GPR[rt]31..24, GPR[rs]2..0 )
tempC7..0 = shift8Right( GPR[rt]23..16, GPR[rs]2..0 )
tempB7..0 = shift8Right( GPR[rt]15..8, GPR[rs]2..0 )
tempA7..0 = shift8Right( GPR[rt]7..0, GPR[rs]2..0 )
GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0

Exceptions:

Reserved Instruction, DSP Disabled