|
POOL32A 000000 |
rt |
rs |
rd |
bp |
000 |
ALIGN 011111 |
|
6 |
5 |
5 |
5 |
2 |
3 |
6 |
|
POOL32S 010110 |
rt |
rs |
rd |
bp |
00 |
DALIGN 011100 |
|
6 |
5 |
5 |
5 |
3 |
2 |
6 |
ALIGN DALIGN |
Concatenate two GPRs, and extract a contiguous subset at a byte position | |
ALIGN rd,rs,rt,bp |
microMIPS32 Release 6 |
Concatenate two GPRs, and extract a contiguous subset at a byte position |
DALIGN rd,rs,rt,bp |
microMIPS64 Release 6 |
Concatenate two GPRs, and extract a contiguous subset at a byte position |
Concatenate two GPRs, and extract a contiguous subset at a byte position
GPR[rd] = (GPR[rt] << (8*bp)) or (GPR[rs] >> (GPRLEN-8*bp))
The input registers GPR rt and GPR rs are concatenated, and a register width contiguous subset is extracted, which is specified by the byte pointer bp.
The ALIGN instruction operates on 32-bit words, and has a 2-bit byte position field bp.
The DALIGN instruction operates on 64-bit doublewords, and has a 3-bit byte position field bp.
ALIGN: The rightmost 32-bit word in GPR rt is left shifted as a 32-bit value by bp byte positions. The rightmost
32-bit word in register rs is right shifted as a 32-bit value by (4-bp) byte positions. These shifts are logical shifts, zero-filling. The shifted values are then or-ed together to create a 32-bit result that is sign-extended to 64bits and written to destination GPR rd.
DALIGN: The 64-bit doubleword in GPR rt is left shifted as a 64 bit value by bp byte positions. The 64-bit word in register rs is right shifted as a 64-bit value by (8-bp) byte positions. These shifts are logical shifts, zero-filling. The shifted values are then or-ed together to create a 64-bit result and written to destination GPR rd.
Executing ALIGN and DALIGN with shift count bp=0 acts like a register to register move operation, and is redundant, and therefore discouraged. Software should not generate ALIGN or DALIGN with shift count bp=0.
DALIGN: A Reserved Instruction exception is signaled if access to 64-bit operations is not enabled.
The ALIGN instruction is introduced by and required as of Release 6.
The DALIGN instruction is introduced by and required as of Release 6.
Release 6 ALIGN instruction corresponds to the pre-Release 6 DSP Module BALIGN instruction, except that
BALIGN with shift counts of 0 and 2 are specified as being UNPREDICTABLE, whereas ALIGN (and DALIGN) defines all bp values, discouraging only bp=0.
Graphically,