Encoding:

Format:

SELEQZ SELNEZ 

SELEQZ rd,rs,rt

SELNEZ rd,rs,rt

Purpose:

Select integer GPR value or zero

Description:

SELEQZ: GPR[rd] = GPR[rt] ? 0 : GPR[rs]
SELNEZ: GPR[rd] = GPR[rt] ? GPR[rs] : 0

• SELEQZ is a select operation, with a condition input in GPR rt, one explicit data input in GPR rs, and implicit data input 0. The condition is true only if all bits in GPR rt are zero.

• SELNEZ is a select operation, with a condition input in GPR rt, one explicit data input in GPR rs, and implicit data input 0. The condition is true only if any bit in GPR rt is nonzero

If the condition is true, the value of rs is written to rd.

If the condition is false, the zero written to rd.

This instruction operates on all GPRLEN bits of the CPU registers, that is, all 32 bits on a 32-bit CPU, and all 64 bits on a 64-bit CPU. All GPRLEN bits of rt are tested.

Restrictions:

None

Availability and Compatibility:

These instructions are introduced by and required as of MIPS32 Release 6.

Special Considerations:

None

Operation:

SELNEZ: cond = GPR[rt] != 0
SELEQZ: cond = GPR[rt] = 0
if cond then
   tmp = GPR[rs]
else
   tmp = 0
endif
GPR[rd] = tmp

Exceptions:

None

Programming Note:

Release 6 removes the Pre-Release 6 instructions MOVZ and MOVN:

MOVZ: if GPR[rt] = 0 then GPR[rd] = GPR[rs] 
MOVN: if GPR[rt] != 0 then GPR[rd] = GPR[rs] 

MOVZ can be emulated using Release 6 instructions as follows:

SELEQZ at, rs, rt
SELNEZ rd, rd, rt
OR rd, rd, at

Similarly MOVN:

SELNEZ at, rs, rt
SELEQZ rd, rd, rt
OR rd, rd, at

The more general select operation requires 4 registers (1 output + 3 inputs (1 condition + 2 data)) and can be expressed:

rD = if rC then rA else rB

The more general select can be created using Release 6 instructions as follows:

SELNEZ at, rB, rC
SELNEZ rD, rA, rC
OR rD, rD, at