Encoding:

Format:

TLBGINV

Purpose:

Guest TLB Invalidate

Index match. The virtual address isTLBGINV invalidates a set of guest TLB entries based on ASID and guest ignored in the match.

Implementation of the TLBGINV instruction is optional. The implementation of this instruction is indicated by the IE field in Config4.

Implementation of EntryHI_EHINV field is required for implementation of TLBGINV instruction.

Support for TLBGINV is recommended for implementations supporting VTLB/FTLB type TLB’s.

Description:

On execution ofthe TLBGINV instruction,the set of guest TLB entries with matching ASID are marked invalid, excluding those guest TLB entries which have their G bit set to 1.

The EntryHI_ASID field has to be set to the appropriate ASID value before executing the TLBGINV instruction.

Behavior of the TLBGINV instruction applies to all applicable guest TLB entries and is unaffected by the setting of the Guest.Wired register.

For JTLB-based MMU(Config_MT=1):

All matching entries in the guest JTLB are invalidated. Index is unused.

For VTLB/FTLB -based MMU(Config_MT=4):

A TLBGINV with Index set in guest VTLB range causes all matching entries in the guest VTLB to be invalidated. A TLBGINV with Index set in guest FTLB range causes all matching entries in the single addressed guest

FTLB set to be invalidated.

If TLB invalidate walk is implemented in software (Config4_IE=2), then software must do these steps:

1.one TLBGINV instruction is executed with an index in guest VTLB range (invalidates all matching guest

VTLB entries)

2.a TLBGINV instruction is executed for each guest FTLB set (invalidates all matching entries in guest FTLB set)

If TLB invalidate walk is implemented in hardware (Config4_IE=3), then software must do these steps:

1.one TLBGINV instruction is executed (invalidates all matching entries in both guest FTLB & guest VTLB).

In this case, Index is unused.

In an implementation supporting GuestID (GuestCtl0_G1=1), matching of guest TLB entries includes comparison of the TLB entry GuestID with the Root GuestID control field, GuestCtl1RID .

Note that the TLBGINV instruction only invalidates guest virtual address translations in the guest TLB, invalidation of guest physical address translations requires execution of the equivalent TLBINV instruction sequence in the root

TLB.

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of available TLB entries (for the case of ConfigMT=4).

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

For processors that do not include a TLB, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

   if (Guest.ConfigMT=1 or
      (Guest.ConfigMT=4 & Guest.Cοnfig4IE=2 & Index≤ Guest.Config1MMU_SIZE-1))
      startnum = 0
      endnum = Guest.Config1MMU_SIZE-1
   endif
   // treating VTLB and FTLB as one array
   if (Guest.ConfigMT=4 & Guest.Cοnfig4IE=2 & Index > Guest.Config1MMU_SIZE-1)
      startnum = start of selected Guest FTLB set // implementation specific
      endnum = end of selected Guest FTLB set - 1 //implementation specifc
   endif
   if (Guest.ConfigMT=4 & Guest.Cοnfig4IE=3))
      startnum = 0
      endnum = Guest.Config1MMU_SIZE-1 +
      ((Guest.Config4FTLBWays + 2) * Guest.Config4FTLBSets)
   endif
   if IsCoprocessorEnabled(0) then
      for (i = startnum to endnum)
         if ((Guest.TLB[i]ASID = Guest.EntryHiASID) & (Guest.TLB[i]G = 0))
             if (GuestCtl0G1 = 1)
                if (Guest.TLB[i]GuestID = GuestCtl1RID)
                   Guest.TLB[i]hardware_invalid = 1
                endif
             else
                   Guest.TLB[i]hardware_invalid = 1
             endif
         endif
      endfor
   else
      SignalException(CoprocessorUnusable, 0)
   endif

Exceptions:

Coprocessor Unusable

Reserved Instruction