Encoding:

Format:

MULEU_S.PH.QBL rd, rs, rt

Purpose:

Multiply Unsigned Vector Left Bytes by Halfwords to Halfword Products

Multiply two left-most unsigned byte vector elements in a four-element byte vector by two unsigned halfword vector elements to produce two unsigned halfword results, with saturation.

Description:

rd = sign_extend(sat16(rs31..24 * rt31..16) || sat16(rs23..16 * rt15..0))

The two left-most unsigned byte elements in the right-mostfour-element byte vector in register rs are multiplied as unsigned integer values with the four corresponding unsigned halfword elements from register rt. The eight most-significant bits of each 24-bit result are di scarded, and the remaining 16 least-s ignificant bits are written to the corresponding elements in halfword vector register rd. The instruction saturates the result to the maximum positive value

(0xFFFF hexadecimal) if any of the discarded bits from each intermediate result are non-zero.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators, ac1, ac2, and ac3 are unmodified.

If either result is saturated this instruction writes a 1 to bit 21 in the DSPControl register in the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = multiplyU8U16( GPR[rs]31..24, GPR[rt]31..16 )
tempA15..0 = multiplyU8U16( GPR[rs]23..16, GPR[rt]15..0 )
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0 
HI[0]63..0 = UNPREDICTABLE
LO[0]63..0 = UNPREDICTABLE
function multiplyU8U16( a7..0, b15..0 )
   temp25..0 = (0 || a) * (0 || b)
   if ( temp25..16> 0x00 ) then
      temp25..0 = 010 || 0xFFFF
      DSPControlouflag:21 = 1
   endif
   return temp15..0
endfunction multiplyU8U16

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS64 architecture states that after a GPR-targeting multiply instruction such as MUL, the contents of registers HI and LO are UNPREDICTABLE. To maintain compliance with the base architecture this multiply instruction, MULEU_S.PH.QBL, has the same requirement. Software must save and restore the ac0 register if the previous value in the ac0 register is needed following the MULEU_S.PH.QBL instruction.

Note that the requirement on HI and LO does not apply to the new accumulator registers ac1, ac2, and ac3; as a result the values in these accumulators need not be saved.