Encoding:

SH16

101010

rt

base

offset

6

3

3

4

Format: 

SH16 rt, left_shifted_offset(base)

microMIPS

Store Halfword (16-bit instr size)

Purpose:

Store Halfword (16-bit instr size)

To store a halfword to memory

Description: 

 memory[GPR[base] + (offset <= 2)] = GPR[rt]

The least-significant 16-bit halfword of register rt is stored in memory at the location specified by the aligned effective address. The 4-bit unsigned offset is left shifted by one bit and then added to the contents of GPR base to form the effective address.

Restrictions:

The 3-bit base register field can only specify GPRs $2-$7, $16, $17.

The 3-bit rt register field can only specify GPRs $0, $2-$7, $17.

Pre-Release 6: The effective address must be naturally-aligned. If the least-significant bit of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation: 

vAddr = zero_extend(offset|| 0) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian2 || 0))
bytesel = vAddr2..0 xor (BigEndianCPU2 || 0)
datadoubleword = GPR[rt]63-8*bytesel..0 || 08*bytesel
StoreMemory (CCA, HALFWORD, datadoubleword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch