Encoding:

POOL32A

000000

rt

rs

0

00000

0

CMPU.LE.QB

1011000101

POOL32A

000000

rt

rs

0

00000

0

CMPU.LT.QB

1010000101

POOL32A

000000

rt

rs

0

00000

0

CMPU.EQ.QB

1001000101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

0

00000

CMPU.EQ.QB

00000

CMPU.EQ.QB

010001

SPECIAL3

011111

rs

rt

0

00000

CMPU.LT.QB

00001

CMPU.EQ.QB

010001

SPECIAL3

011111

rs

rt

0

00000

CMPU.LE.QB

00010

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format: 

CMPU.cond.QB

Compare Vectors of Unsigned Byte Values

CMPU.EQ.QB  rs, rt

microMIPSDSP

Compare Vectors of Unsigned Byte Values

CMPU.LT.QB  rs, rt

microMIPSDSP

Compare Vectors of Unsigned Byte Values

CMPU.LE.QB  rs, rt

microMIPSDSP

Compare Vectors of Unsigned Byte Values

Purpose:

Compare Vectors of Unsigned Byte Values

Perform an element-wise comparison of two vectors of four unsigned bytes, recording the results of the comparison in condition code bits.

Description: 

DSPControlccond:27..24 = (rs31..24 cond rt31..24) || (rs23..16 cond rt23..16) || (rs15..8 cond rt15..8) || (rs7..0 cond rt7..0)

Each of the four right-most unsigned byte elements in register rs are compared with the corresponding unsigned byte elements in register rt. The four 1-bit boolean comparison results are written to bits 24 through 27 of the DSPControl register's 8-bit condition code field. The value of bits 28 through 31 of the DSPControl register's condition code field are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

CMPU.EQ.QB:
   ccD = GPR[rs]31..24 EQ GPR[rt]31..24 
   ccC = GPR[rs]23..16 EQ GPR[rt]23..16 
   ccB = GPR[rs]15..8 EQ GPR[rt]15..8 
   ccA = GPR[rs]7..0 EQ GPR[rt]7..0 
   DSPControlccond:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
CMPU.LT.QB:
   ccD = GPR[rs]31..24 LT GPR[rt]31..24 
   ccC = GPR[rs]23..16 LT GPR[rt]23..16 
   ccB = GPR[rs]15..8 LT GPR[rt]15..8 
   ccA = GPR[rs]7..0 LT GPR[rt]7..0 
   DSPControlccond:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
CMPU.LE.QB:
   ccD = GPR[rs]31..24 LE GPR[rt]31..24 
   ccC = GPR[rs]23..16 LE GPR[rt]23..16 
   ccB = GPR[rs]15..8 LE GPR[rt]15..8 
   ccA = GPR[rs]7..0 LE GPR[rt]7..0 
   DSPControlccond:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE

Exceptions:

Reserved Instruction, DSP Disabled