Encoding:

Format:

BC2EQZC BC2NEZC 

BC2EQZC ct, offset 

BC2NEZC ct, offset 

Purpose:

Branch if Coprocessor 2 Condition (Register) Equal/Not Equal to Zero

BC2EQZC: Branch if Coprocessor 2 Condition (Register) is Equal to Zero

BC2NEZC: Branch if Coprocessor 2 Condition (Register) is Not Equal to Zero

Description:

BC2EQZC:  if COP2Condition[ct] = 0 then branch
BC2NEZC:  if COP2Condition[ct] != 0 then branch

The 5-bit field ct specifies a coprocessor 2 condition.

• For BC2EQZC if the coprocessor 2 condition is true the branch is taken.

• For BC2NEZC if the coprocessor 2 condition is false the branch is taken.

A 17-bit signed offset (the 16-bit offset field shifted left 1 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.

Compact branches do not have delay slots. The instruction after the branch is NOT executed if the branch is taken.

Restrictions:

Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.

If access to Coprocessor 2 is not enabled, a Coprocessor Unusable Exception is signaled.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

Exceptions:

Coprocessor Unusable, Reserved Instruction

Operation:

   tmpcond = Coprocessor2Condition(ct)
   if BC2EQZC then 
    tmpcond = not(tmpcond)
   endif
   if tmpcond then
      PC = PC+4 + sign_extend( immediate << 1 ) )
   endif

Implementation Notes:

As of Release 6 these instructions, BC2EQZC and BC2NEZC, replace the pre-Release 6 instructions BC2F and

BC2T, which had a 3-bit condition code field (as well as nullify and true/false bits). Release 6 makes all 5 bits of the

ct condition code available to the coprocessor designer as a condition specifier.

A customer defined coprocessor instruction set can implement any sort of condition it wants. For example, it could implement up to 32 single-bit flags, specified by the 5-bit field ct. It could also implement conditions encoded as values in a coprocessor register (such as testing the least significant bit of a coprocessor register) as done by Release

6 instructions BC1EQZ/BC1NEZ.