Encoding:

Format:

TLBGP

Purpose:

Probe Guest TLB for Matching Entry

To ind a matching entry in the Guest TLB, initiated from root mode.

Description:

The Guest.Index register is loaded with the address of the Guest TLB entry whose contents match the contents of the

Guest.EntryHi register. If no Guest TLB entry matches, the high-order bit of the Guest.Index register is set.

In an implementation supporting GuestID (GuestCtl0_G1=1), if the GuestID read does not match GuestCtl1_RID, then the match fails.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

If an implementation detects multiple matches, and does not detect all multiple matches on TLB write, then a TLBGP instruction can take a Machine Check Exception if multiple matches occur.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3VZ = 0) then
       SignalException(ReservedInstruction, 0)
       break
   endif
   Guest.Index = 1 || UNPREDICTABLE31
// If a set-associative TLB is used, then a single set may be probed.
for i in 0...Guest.TLBEntries-1
      if (((Guest.TLB[i]VPN2 and ~(Guest.TLB[i]Mask)) =
             (Guest.EntryHiVPN2 and ~(Guest.TLB[i]Mask))) and
             (Guest.TLB[i]R = Guest.EntryHiR) and
             ((Config4IE >= 2)and not TLB[i]hardware_invalid) and
             (Guest.TLB[i]G or (Guest.TLB[i]ASID = Guest.EntryHiASID))) then
                   if (GuestCtl0G1 = 1)
                          if (Guest.TLB[i]GuestID = GuestCtl1RID)
                                 Guest.Index = i
                          endif
                   else
                       Guest.Index = i
                endif
         endif
   endfor
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Machine Check (implementation dependent)

Reserved Instruction