Encoding:

Format:

SDP rd, offset(base)

Purpose:

Store Doubleword Pair

To store two consecutive doublewords to memory

Description:

 memory[GPR[base] + offset] = GPR[rd], GPR[rd+1]

The contents of the 64-bit doublewords of GPR rd and GPR rd+1 are stored in memory at the location specified by the aligned effective address. The 12-bit signed offset is added to the contents of GPR base to form the effective address.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Restrictions:

The behavior of the instructions is UNDEFINED if rd equals $31.

Pre-Release 6: The effective address must be naturally aligned. If any of the 3 least-significant bits of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation:

if Are64bitOperationsEnabled() then
   vAddr = sign_extend(offset) + GPR[base]
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)==
   datadoubleword = GPR[rd]
   StoreMemory (CCA, DOUBLEWORD, datadoubleword, pAddr, vAddr, DATA)
   vAddr = sign_extend(offset) + GPR[base] + 8
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)==
   datadoubleword = GPR[rd+1]
   StoreMemory (CCA, DOUBLEWORD, datadoubleword, pAddr, vAddr, DATA)
else
   SignalException(ReservedInstruction)
endif

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Address Error, Reserved Instruction, Watch

Programming Notes:

This instruction may execute for a variable number of cycles and may perform a variable number of stores to memory.

A full restart of the sequence of operations will be performed on return from any exception taken during execution.