Encoding:

Format:

BC1EQZC BC1NEZC 

BC1EQZC ft, offset 

BC1NEZC ft, offset 

Purpose:

Branch if Coprocessor 1 (FPU) Register Bit 0 Equal/Not Equal to Zero

BC1EQZC: Branch if Coprocessor 1 (FPU) Register Bit 0 is Equal to Zero

BC1NEZC: Branch if Coprocessor 1 (FPR) Register Bit 0 is Not Equal to Zero

Description:

BC1EQZC:  if FPR[ft] & 1 = 0 then branch
BC1NEZC:  if FPR[ft] & 1 != 0 then branch

The condition is evaluated on FPU register ft.

• For BC1EQZC, the condition is true if and only if bit 0 of the FPU register ft is zero.

• For BC1NEZC, the condition is true if and only if bit 0 of the FPU register ft is non-zero.

If the condition is false, the branch is not taken, and execution continues with the next instruction.

A 17-bit signed offset (the 16-bit offset field shifted left 1 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.

Compact branches do not have delay slots. The instruction after the branch is NOT executed if the branch is taken.

Restrictions:

If access to Coprocessor 1 is not enabled, a Coprocessor Unusable Exception is signaled.

Because these instructions BC1EQZC and BC1NEZC do not depend on a particular floating point data type, they operate whenever Coprocessor 1 is enabled.

Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

Exceptions:

Coprocessor Unusable¹

Operation:

   tmp = ValueFPR(ft, UNINTERPRETED_WORD)
   BC1EQZC: cond = tmp & 1 = 0
   BC1NEZC: cond = tmp & 1 != 0
   if cond then
          target_PC = ( PC+4 + sign_extend( offset << 1 )
          PC = target_PC

Programming Notes:

Release 6: These instructions, BC1EQZC and BC1NEZC, replace the pre-Release 6 instructions BC1F and BC1T.

These Release 6 FPU branches depend on bit 0 of the scalar FPU register.

Note: BC1EQZC and BC1NEZC do not have a format or data type width. The same instructions are used for branches based on conditions involving any format, including 32-bit S (single precision) and W (word) format, and

64-bit D (double precision) and L (longword) format, as well as 128-bit MSA. The FPU scalar comparison instructions CMP.condn fmt produce an all ones or all zeros truth mask of their format width with the upper bits (where applicable) UNPREDICTABLE. BC1EQZ and BC1NEZ consume only bit 0 of the CMP.condn.fmt output value, and therefore operate correctly independent of fmt.