POOL32A 000000 |
rt |
rs |
rd |
0 |
SUBQ_S.W 1101000101 |
6 |
5 |
5 |
5 |
1 |
10 |
SPECIAL3 011111 |
rs |
rt |
rd |
SUBQ_S.W 10111 |
ADDU.QB 010000 |
6 |
5 |
5 |
5 |
5 |
6 |
SUBQ_S.W rd, rs, rt |
microMIPSDSP |
Subtract Fractional Word |
Subtract Fractional Word
One Q31 fractional word is subtracted from another to produce a Q31 fractional result, with saturation.
rd = sign_extend(sat32(rs31..0 - rt31..0))
The right-mostQ31 fractional word in register rt is subtracted from the corresponding fractional word in register rs, and the 32-bit result is sign-extended to 64 bits and written to destination register rd. The subtraction is performed using signed saturating arithmetic. If the operation results in an overflow or an underflow, the result is clamped to either the largest representable value (0x7FFFFFFF hexadecimal) or the smallest representable value (0x80000000 hexadecimal), respectively, before being sign-extended and written to the destination register rd.
If the subtraction results in underflow, overflow, or saturation, a 1 is writ ten to bit 20 in the DSPControl register within the ouflag field.
No data-dependent exceptions are possible.
The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
temp31..0 = sat32Subtract( GPR[rs]31..0 , GPR[rt]31..0 ) GPR[rd]63..0 = (temp31)32 || temp31..0 function sat32Subtract( a31..0, b31..0 ) temp32..0 = ( a31 || a31..0 ) - ( b31 || b31..0 ) if ( temp32 != temp31) then if ( temp32 = 0 ) then temp31..0 = 0x7FFFFFFF else temp31..0 = 0x80000000 endif DSPControlouflag:20 = 1 endif return temp31..0 endfunction sat32Subtract
Reserved Instruction, DSP Disabled