POOL32B 001000 |
rt |
base |
LDC2 0010 |
0 0 |
offset |
6 |
5 |
5 |
4 |
1 |
11 |
LDC2 rt, offset(base) |
microMIPS |
Load Doubleword to Coprocessor 2 |
Load Doubleword to Coprocessor 2
To load a doubleword from memory to a Coprocessor 2 register.
CPR[2,rt,0] = memory[GPR[base] + offset]
The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed in Coprocessor 2 register rt. The 9-bit signed offset is added to the contents of GPR base to form the effective address.
Pre-Release 6: An Address Error exception occurs if EffectiveAddress2..0 != 0 (not doubleword-aligned).
Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.
Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.
vAddr = sign_extend(offset) + GPR[base] (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD) memdoubleword = LoadMemory(CCA, DOUBLEWORD, pAddr, vAddr, DATA) CPR[2,rt,0] = memdoubleword
Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, Address Error, Watch
There is no Load Linked Word Unsigned operation corresponding to Load Word Unsigned.
Release 6 implements a 9-bit offset, whereas all release levels lower than Release 6 implement a 16-bit offset.