Encoding:

Format:

SWP rs1, offset(base)

Purpose:

Store Word Pair

To store two consecutive words to memory

Description:

 memory[GPR[base] + offset] = GPR[rs1], GPR[rs1+1]

The least-significant 32-bit words of GPR rs1 and GPR rs1+1 are stored in memory at the location specified by the aligned effective address. The 12-bit signed offset is added to the contents of GPR base to form the effective address.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Restrictions:

The behavior of the instructions is UNDEFINED if rd equals $31.

Pre-Release 6: The effective address must be 32-bit aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
bytesel = vAddr2..0 xor (BigEndianCPU || 02)
datadoubleword = GPR[rs1]63-8*bytesel..0 || 08*bytesel
StoreMemory (CCA, WORD, datadoubleword, pAddr, vAddr, DATA)
vAddr = sign_extend(offset) + GPR[base] + 4
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
bytesel = vAddr2..0 xor (BigEndianCPU || 02)
datadoubleword = GPR[rs1+1]63-8*bytesel..0 || 08*bytesel
StoreMemory (CCA, WORD, datadoubleword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch