Encoding:

POOL32A

000000

index

base

rd

0

LHX

0101100101

6

5

5

5

1

10

SPECIAL3

011111

base

index

rd

LHX

00100

LX

001010

6

5

5

5

5

6

Format: 

LHX rd, index(base)

microMIPSDSP

Load Halfword Indexed

Purpose:

Load Halfword Indexed

To load a halfword value from memory as a signed value, using indexed addressing.

Description: 

 rd = memory[base+index]

The contents of GPR index is added to the contents of GPR base to form an effective address. The contents of the 16bit halfword at the memory location specified by the aligned effective address are fetched, sign-extended to the length of the destination GPR, and placed in GPR rd.

Restrictions:

The effective address must be naturally-aligned. If the l east-significant bit of the effective address is non-zero, an

Address Error exception occurs.

Operation: 

vAddr31..0 = GPR[index]31..0 + GPR[base]31..0
if ( vAddr0 != 0 ) then
   SignalException( AddressError )
endif
( pAddr, CCA ) = AddressTranslation( vAddr, DATA, LOAD )
halfwordGPRLEN..0 = LoadMemory( CCA, HALFWORD, pAddr, vAddr, DATA )
GPR[rd]63..0 = sign_extend( halfword15..0 )

Exceptions:

Reserved Instruction, DSP Disabled, TLB Refill, TLB Invalid, Bus Error, Address Error, Watch