POOL32A 000000 |
rt |
rs |
ac |
DPSQX_S.W.PH 10011010 |
POOL32Axf 111100 |
6 |
5 |
5 |
2 |
8 |
6 |
SPECIAL3 011111 |
rs |
rt |
0 000 |
ac |
DPSQX_S.W.PH 11001 |
DPA.W.PH 110000 |
6 |
5 |
5 |
3 |
2 |
5 |
6 |
DPSQX_S.W.PH ac, rs, rt |
microMIPSDSP-R2 |
Cross Dot Product with Subtraction on Fractional Halfword Elements |
Cross Dot Product with Subtraction on Fractional Halfword Elements
Element-wise cross multiplication of two vectors of fractional halfword elements and subtraction of the accumulated
32-bit intermediate products from the specified 64-bit accumulator register, with saturation.
ac = ac - (sat32(rs31..16 * rt15..0) + sat32(rs15..0 * rt31..16))
The left of the right-most Q15 fractional word values from registers rt is multiplied with the right halfword element from register rs and the result left-shifted by one bit position to generate a Q31 fractional format intermediate product. Similarly, the right of the right-most Q15 fractional word values from registers rt is multiplied with the left halfrs and the result left-shifted by one bit word element from register position to generate a Q3 1 fractional format intermediate product. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).
The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is subtracted from the specified 64-bit HI/LO accumulator to produce a final Q32.31 fractional result.
The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.
If saturation occurs as a result of a h alfword multiplication, a 1 is written to o ne of bits 1 6 through 19 of the
DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds
to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.
No data-dependent exceptions are possible.
The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]15..0 ) tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]31..16 ) dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 ) tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0 ( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0 function multiplyQ15Q15( acc1..0, a15..0, b15..0 ) if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then temp31..0 = 0x7FFFFFFF DSPControlouflag:16+acc = 1 else temp31..0 = ( a15..0 * b15..0 ) << 1 endif return temp31..0 endfunction multiplyQ15Q15
Reserved Instruction, DSP Disabled