Encoding:

Format:

TLBGR

Purpose:

Read Indexed Guest TLB Entry

To read an entry from the Guest TLB into the guest context, initiated from root mode.

Description:

The Guest.EntryHi, Guest.EntryLo0, Guest.EntryLo1, and Guest.PageMask registers are loaded with the conthe Guest.Index tents of the Guest TLB entry pointed to by register. Note that the value written to the

Guest.EntryHi, Guest.EntryLo0, and Guest.EntryLo1 registers may be different from that originally written to the

TLB via these registers in that:

The value returned in the VPN2 ield of the EntryHi register may have those bits set to zero corresponding to the

• one bits in the Mask ield of the TLB entry (the least signiicant bit of VPN2 corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.

The value returned in the PFN ield of the EntryLo0 and EntryLo1 registers may have those bits set to zero cor-

• responding to the one bits in the Mask ield of the TLB entry (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.

The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the

• TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written. the GuestCtl1RID ield is written

In an implementation supporting GuestID,if the TLB entry is not marked invalid, with the GuestID of the TLB entry read.

Restrictions:

The operation is UNDEFINED if the contents of the Guest.Index register are greater than or equal to the number of

TLB entries in the guest context.

If root-mode access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   i = Guest.Index
   if i > (Guest.TLBEntries - 1) then
      UNDEFINED
   endif
   if (Config4IE >= 2 && Guest.TLB[i]EHINV = 1) then
      GuestCtl1RID = 0
      Guest.PagemaskMask = 0
      Guest.EntryHi = 0
      Guest.EntryLo1 = 0
      Guest.EntryLo0 = 0
      Guest.EntryHiEHINV = 1
      break
   endif
   if (GuestCtl0G1 = 1)
      GuestCtl1RID = Guest.TLB[i]GuestID
   endif
   Guest.PageMaskMask = Guest.TLB[i]Mask
   Guest.EntryHi = Guest.TLB[i]R || 0Fill ||
         (Guest.TLB[i]VPN2 and not Guest.TLB[i]Mask) || # Masking impl dependent
         05 || Guest.TLB[i]ASID
   Guest.EntryLo1 = 0Fill ||
         (Guest.TLB[i]PFN1 and not Guest.TLB[i]Mask) || # Masking impl dependent
         Guest.TLB[i]C1 || Guest.TLB[i]D1 || Guest.TLB[i]V1 || Guest.TLB[i]G
   Guest.EntryLo0 = 0Fill ||
         (Guest.TLB[i]PFN0 and not Guest.TLB[i]Mask) || # Masking impl dependent
         Guest.TLB[i]C0 || Guest.TLB[i]D0 || Guest.TLB[i]V0 || Guest.TLB[i]G
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction