Encoding:

Format:

DPSU.H.QBR ac, rs, rt

Purpose:

Dot Product with Subtraction on Vector Unsigned Byte Elements

Element-wise multiplication of the two right-most elements of the four right-most elements of each of two vectors of unsigned bytes, subtracting the sum of the products from the specified 64-bit accumulator register.

Description:

ac = ac - zero_extend((rs15..8 * rt15..8) + (rs7..0 * rt7..0))

The two right-most elements of the four right-most uns igned byte elements of each of registers rt and rs are multiplied together using unsigned arithmetic to generate tw o 16-bit unsigned intermediate products. The intermediate products are then zero-extended to 64 bits and subtracted from the specified 64-bit HI/LO accumulator.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = multiplyU8U8( GPR[rs]15..8, GPR[rt]15..8 )
tempA15..0 = multiplyU8U8( GPR[rs]7..0, GPR[rt]7..0 )
dotp63..0 = ( 048 || tempB15..0 ) + ( 048 || tempA15..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0 

Exceptions:

Reserved Instruction, DSP Disabled