Encoding:

Format:

LLWPE rt, rd, (base)

Purpose:

Load Linked Word Paired EVA

To load two words from memory for an atomic read-modify-write, writing a word each to two registers. The load occurs in kernel mode from user virtual address space.

Description:

 GPR[rd] = memory[GPR[base]]63..32, GPR[rt] = memory[GPR[base]]31..0

The LLWPE and SCWPE instructions provide primitives to implement a paired word atomic read-modify-write

(RMW) operation at a synchronizable memory location.

The 64-bit paired word at the memory location specified by the double-word aligned effective address is read. The least significant word, sign-extended to the GPR register length, is written into GPR rt. The most significant word, sign-extended to the GPR register length, is written into GPR rd.

A paired word read or write occurs as a pair of word reads or writes that is double-word atomic.

The instruction has no offset. The effective address is equal to the contents of GPR base.

rd is intentionally positioned in a non-standard bit-range.

The execution of LLWPE begins a RMW sequence on the current processor. There can be only one active RMW sequence per processor. When an LLWPE is executed it starts an active RMW sequence replacing any other sequence that was active. The RMW sequence is completed by a subsequent SCWPE instruction that either completes the

RMW sequence atomically and succeeds, or does not and fails.

Successful execution of the LLWPE results in setting LLbit and writing CP0 LLAddr, where LLbit is the least-significant bit of LLAddr. LLAddr contains the data-type aligned address of the operation, in this case a double-word aligned address.

The LLWPE instruction functions the same as the LLWP instruction, except that address translation is performed using the user mode virtual address space mapping in the TLB when accessing an address within a memory segment configured to use the MUSUK access mode. Memory segments using UUSK or MUSK access modes are also accessible. Refer to Volume III, Segmentation Control for additional information.

Executing LLWPE on one processor does not cause an action that, by itself, causes a store conditional instruction type for the same block to fail on another processor.

An execution of LLWPE does not have to be followed by execution of SCWPE; a program is free to abandon the

RMW sequence without attempting a write.

Restrictions:

The addressed location must be synchronizable by all processors and I/O devices sharing the location; if it is not, the result is UNPREDICTABLE. Which storage is synchronizable is a function of both CPU and system implementations. See the documentation of the SC instruction for the formal definition.

The architecture optionally allows support for Load-Linked and Store-Conditional instruction types in a cacheless processor. Support for cacheless operation is implementation dependent. In this case, LLAddr is optional.

Providing misaligned support is not a requirement for this instruction.

Availability and Compatibility

This instruction is introduced by Release 6. It is only present if Config5_XNP=0 and Config5_EVA=1.

Operation:

vAddr = GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
// PAIREDWORD: two word data-type that is double-word atomic
memdoubleword = LoadMemory (CCA, PAIREDWORD, pAddr, vAddr, DATA)
GPR[rt] = sign_extend(memdoubleword31..0)
GPR[rd] = sign_extend(memdoubleword63..32)
LLAddr = pAddr // double-word aligned i.e., pAddr2..0 are 0, or not supported.
LLbit = 1

Exceptions:

TLB Refill, TLB Invalid, Reserved Instruction, Address Error, Watch, Coprocessor Unusable.

Programming Notes:

An LLWPE instruction for which the two destination registers are the same but non-zero is UNPREDICTABLE. An

LLWPE with two zero destination registers followed by a SCWPE can be used to accomplish a double-word atomic write.