|
POP35 |
BOVC rs >=rt |
offset | |
|
011101 |
rt |
rs |
|
|
POP37 |
BNVC rs>=rt |
offset | |
|
011111 |
rt |
rs |
|
|
6 |
5 |
5 |
16 |
BOVC BNVC |
Detect overflow for add (signed 32 bits) and branch if overflow. | |
BOVC rt,rs, offset |
microMIPS32 Release 6 |
Detect overflow for add (signed 32 bits) and branch if overflow. |
BNVC rt,rs, offset |
microMIPS32 Release 6 |
Detect overflow for add (signed 32 bits) and branch if no overflow. |
Branch on Overflow, Compact; Branch on No Overflow, Compact
BOVC: Detect overflow for add (signed 32 bits) and branch if overflow.
BNVC: Detect overflow for add (signed 32 bits) and branch if no overflow.
branch if/if-not NotWordValue(GPR[rs]+GPR[rt])
BOVC performs a signed 32-bit addition of rs and rt. BOVC discards the sum, but detects signed 32-bit integer overflow of the sum (and the inputs, in MIPS64), and branches if such overflow is detected.
BNVC performs a signed 32-bit addition of rs and rt. BNVC discards the sum, but detects signed 32-bit integer overflow of the sum (and the inputs, in MIPS64), and branches if such overflow is not detected.
A 17-bit signed offset (the 16-bit offset field shifted left 1 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
On 64-bit processors, BOVC and BNVC detect signed 32-bit overflow on the input registers as well as the output.
This checking is performed even if 64-bit operations are not enabled.
The special case with rt=0 (for example, GPR[0]) is allowed. On MIPS64, this checks that the input value of rs is a well-formed signed 32-bit integer: BOVC rs,r0,offset branches if rs is not a 32-bit integer, and BNVC rs, r0 offset branches if rs is a 32-bit integer.
The special case of rs=0 and rt=0 is allowed. BOVC never branches, while BNVC always branches.
Compact branches do not have delay slots. The instruction after the branch is NOT executed if the branch is taken.
Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.
These instructions are introduced by and required as of Release 6.
input_overflow = NotWordValue(GPR[rs]) or NotWordValue(GPR[rt]) temp1 = sign_extend.32( GPR[rs]31..0 ) temp2 = sign_extend.32( GPR[rt]31..0 ) tempd = temp1 + temp2 // wider than 32-bit precision sum_overflow = (tempd32 != tempd31) BOVC: cond = sum_overflow or input_overflow BNVC: cond = not( sum_overflow or input_overflow ) if cond then PC = ( PC+4 + sign_extend( offset << 1 ) ) endif
None