Encoding:

Format:

TLBWR

Purpose:

Write Random TLB Entry

To write a TLB entry indexed by the Random register.

Description:

The TLB entry pointed to by the Random register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers.

The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:

• The value written to the VPN2 ield of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of the PageMask register (the least signiicant bit of VPN2 corresponds to the least significant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

• The value written to the PFN0 and PFN1 ields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of PageMask register (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 reg-

• isters.

In an implementation supporting GuestID, GuestCtl1_RID is written in the TLB entry.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

On an VTLB/FTLB enabled implementation, if the Pagemask register contains a page size differing from the FTLB page size deined in Conig4, then the write goes into a random entry in the VTLB.

It is implementation dependent whether multiple TLB matches are detected on a TLBWR, though it is recommended.

If a TLB write detects multiple matches, but not necessarily all multiple matches,then a TLB lookup or TLB probe operation should signal a Machine Check Exception on detection of multiple matches.

If multiple match detection is implemented, then on detection, the multiple match should be invalidated and the write completed. No Machine Check Exception should be signaled.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   if (Config4IE = 1) then
      TLB[i]hardware_invalid = 0
      if ( EntryHIEHINV=1 ) then
         TLB[i]hardware_invalid = 1
      endif
   endif
   TLB[i]Mask = PageMaskMask
   TLB[i]R = EntryHiR
   TLB[i]VPN2 = EntryHiVPN2 and not PageMaskMask # Impl. dependent
   TLB[i]ASID = EntryHiASID
   if (GuestCtl0G1) then
      if ((GuestCtl0RAD=0) and IsRootMode() and (GuestCtl1RID != 0))
         TLB[i]G = 1
      else
         TLB[i]G = EntryLo1G and EntryLo0G
      endif
   else
      TLB[i]G = EntryLo1G and EntryLo0G
   endif
   TLB[i]PFN1 = EntryLo1PFN and not PageMaskMask # Impl. dependent
   TLB[i]C1 = EntryLo1C
   TLB[i]D1 = EntryLo1D
   TLB[i]V1 = EntryLo1V
   TLB[i]PFN0 = EntryLo0PFN and not PageMaskMask # Impl. dependent
   TLB[i]C0 = EntryLo0C
   TLB[i]D0 = EntryLo0D
   TLB[i]V0 = EntryLo0V
   if (GuestCtl0G1) then
      TLB[i]GuestID = GuestCtl1RID
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (implementation dependent)