Encoding:

POOL32A

000000

rt

rs

0

000000

CMP.LE.PH

0010000101

POOL32A

000000

rt

rs

0

000000

CMP.LT.PH

0001000101

POOL32A

000000

rt

rs

0

000000

CMP.EQ.PH

0000000101

6

5

5

6

10

SPECIAL3

011111

rs

rt

0

00000

CMP.EQ.PH

01000

CMPU.EQ.QB

010001

SPECIAL3

011111

rs

rt

0

00000

CMP.LT.PH

01001

CMPU.EQ.QB

010001

SPECIAL3

011111

rs

rt

0

00000

CMP.LE.PH

01010

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format: 

CMP.cond.PH

Compare Vectors of Signed Integer Halfword Values

CMP.EQ.PH  rs, rt

microMIPSDSP

Compare Vectors of Signed Integer Halfword Values

CMP.LT.PH  rs, rt

microMIPSDSP

Compare Vectors of Signed Integer Halfword Values

CMP.LE.PH  rs, rt

microMIPSDSP

Compare Vectors of Signed Integer Halfword Values

Purpose:

Compare Vectors of Signed Integer Halfword Values

Perform an element-wise comparison of two vectors of two signed integer halfwords, recording the results of the comparison in condition code bits.

Description: 

DSPControlccond:25..24 = (rs31..16 cond rt31..16) || (rs15..0 cond rt15..0)

The two right-most signed integer halfword elements in register rs are compared with the corresponding signed integer halfword element in register rt. The two 1-bit boolean comparison results are written to bits 24 and 25 of the

DSPControl register’s 8-bit condition code field. The values of the six remaining condition code bits (bits 26 through

31 of the DSPControl register) are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

CMP.EQ.PH:
   ccB = GPR[rs]31..16 EQ GPR[rt]31..16 
   ccA = GPR[rs]15..0 EQ GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:31..26 = UNPREDICTABLE
CMP.LT.PH:
   ccB = GPR[rs]31..16 LT GPR[rt]31..16 
   ccA = GPR[rs]15..0 LT GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:31..26 = UNPREDICTABLE
CMP.LE.PH:
   ccB = GPR[rs]31..16 LE GPR[rt]31..16 
   ccA = GPR[rs]15..0 LE GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:31..26 = UNPREDICTABLE

Exceptions:

Reserved Instruction, DSP Disabled