Encoding:

POOL32A

000000

rt

rs

rd

0

CMPGDU.LE.QB

1000000101

POOL32A

000000

rt

rs

rd

0

CMPGDU.LT.QB

0111000101

POOL32A

000000

rt

rs

rd

0

CMPGDU.EQ.QB

0110000101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

CMPGDU.EQ.QB

11000

CMPU.EQ.QB

010001

SPECIAL3

011111

rs

rt

rd

CMPGDU.LT.QB

11001

CMPU.EQ.QB

010001

SPECIAL3

011111

rs

rt

rd

CMPGDU.LE.QB

11010

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format: 

CMPGDU.cond.QB

Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl

CMPGDU.EQ.QB  rd, rs, rt

microMIPSDSP-R2

Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl

CMPGDU.LT.QB  rd, rs, rt

microMIPSDSP-R2

Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl

CMPGDU.LE.QB  rd, rs, rt

microMIPSDSP-R2

Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl

Purpose:

Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl

Compare two vectors of four unsigned bytes each, recording the comparison results in condition code bits that are written to both the specified destination GPR and the condition code bits in the DSPControl register.

Description: 

DSPControl[ccond]27..24 = (rs31..24 cond rt31..24) || (rs23..16 cond rt23..16) || (rs15..8 cond rt15..8) || (rs7..0 cond rt7..0);
rd = 0(GPRLEN-4) || DSPControl[ccond]27..24

Each of the four right-most unsigned byte elements in register rs are compared with the corresponding unsigned byte elements in register rt. The four 1-bit boolean comparison results are written to the four least-significant bits of destination register rd and to bits 24 through 27 of the DSPControl register's 8-bit condition code field. The remaining bits in destination register rd are set to zero. The value of bits 28 through 31 of the DSPControl register's condition code field are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

CMPGDU.EQ.QB:
   ccD = GPR[rs]31..24 EQ GPR[rt]31..24 
   ccC = GPR[rs]23..16 EQ GPR[rt]23..16 
   ccB = GPR[rs]15..8 EQ GPR[rt]15..8 
   ccA = GPR[rs]7..0 EQ GPR[rt]7..0 
   DSPControlcc:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA
CMPGDU.LT.QB:
   ccD = GPR[rs]31..24 LT GPR[rt]31..24 
   ccC = GPR[rs]23..16 LT GPR[rt]23..16 
   ccB = GPR[rs]15..8 LT GPR[rt]15..8 
   ccA = GPR[rs]7..0 LT GPR[rt]7..0 
   DSPControlcc:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA
CMPGDU.LE.QB:
   ccD = GPR[rs]31..24 LE GPR[rt]31..24 
   ccC = GPR[rs]23..16 LE GPR[rt]23..16 
   ccB = GPR[rs]15..8 LE GPR[rt]15..8 
   ccA = GPR[rs]7..0 LE GPR[rt]7..0 
   DSPControlcc:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA

Exceptions:

Reserved Instruction, DSP Disabled