Encoding:

Format:

MULQ_RS.PH rd, rs, rt

Purpose:

Multiply Vector Fractional Halfwords to Fractional Halfword Products

Multiply Q15 fractional halfword vector elements with rounding and saturation to produce two Q15 fractional halfword results.

Description:

rd = sign_extend(rndQ15(rs31..16 * rt31..16) || rndQ15(rs15..0 * rt15..0))

The two right-most Q15 fractional halfword elements from register rs are separately multiplied by the corresponding

Q15 fractional halfword elements from register rt to produce 32-bit intermediate results. Each intermediate result is left-shifted by one bit position to produce a Q31 fractional value, then rounded by adding 0x00008000 hexadecimal.

The rounded intermediate result is then truncated to a Q15 fractional value and written to the corresponding position in destination register rd.

The sign of the left-most result is extended into the 32 most-significant bits of the destination register.

If the two input values to either multiplication are both -1.0 (0x8000 in hexadecimal), the final halfword result is saturated to the maximum positive Q15 value (0x7FFF in hexadecimal) and rounding and truncation are not performed.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators, ac1, ac2, and ac3 must be unmodified.

If either result is saturated this instruction writes a 1 to bit 21 in the DSPControl register in the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = rndQ15MultiplyQ15Q15( GPR[rs]31..16, GPR[rt]31..16 )
tempA15..0 = rndQ15MultiplyQ15Q15( GPR[rs]15..0, GPR[rt]15..0 )
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0 
HI[0]63..0 = UNPREDICTABLE
LO[0]63..0 = UNPREDICTABLE
function rndQ15MultiplyQ15Q15( a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFF0000
      DSPControlouflag:21 = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
      temp31..0 = temp31..0 + 0x00008000
   endif
   return temp31..16
endfunction rndQ15MultiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS64 architecture states that after a GPR-targeting multiply instruction such as MUL, the contents of registers HI and LO are UNPREDICTABLE. To maintain compliance with the base architecture, this multiply instruction, MULQ_RS.PH, has the same requirement. Software must save and restore the ac0 register if the previous value in the ac0 register is needed following the MULQ_RS.PH instruction.

Note that the requirement on HI and LO does not apply to the new accumulator registers ac1, ac2, and ac3; as a result, the values in these accumulators need not be saved.