Encoding:

Format:

TLBR

Purpose:

Read Indexed TLB Entry

To read an entry from the TLB.

Description:

The TLBR instruction is unmodiied from the base architectural deinition, exceptin an implementation supporting

GuestID:

When executing in Guest mode, if the GuestID read does not match GuestCtl1_ID, then the TLB related CP0 reg-

• isters are zeroed and EHINV is set to 1.

When executing in Root mode and the TLB entry is not marked as invalid, GuestCtl1_RID is set to the GuestID of

• the TLB entry read, else it is set to 0.

Restrictions:

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

For processors that do notinclude the standard TLB MMU, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   i = Index
   if i > (TLBEntries - 1) then
      UNDEFINED
   endif
   if (Config4IE >= 2 && TLB[i]hardware_invalid=1) then
      if GuestCtl0G1=1
         if (GuestCtl0GM=0 or (GuestCtl0GM=1 and (Root.DebugDM=1 or
             Root.StatusERL=1 or Root.StatusEXL=1))) then
                GuestCtl1RID = 0 // RID only updated in root mode
         endif
      endif
      // Remaining state is handled similarly in root and guest modes.
      PagemaskMask = 0
      EntryHi = 0
      EntryLo1 = 0
      EntryLo0 = 0
      EntryHiEHINV = 1
      break
   endif
   PageMaskMask = TLB[i]Mask
   EntryHi = TLB[i]R || 0Fill ||
             (TLB[i]VPN2 and not TLB[i]Mask) || # Masking implementation dependent
   EntryLo1 = 0Fill ||
             (TLB[i]PFN1 and not TLB[i]Mask) || # Masking mplementation dependent
             TLB[i]C1 || TLB[i]D1 || TLB[i]V1 || TLB[i]G
   EntryLo0 = 0Fill ||
             (TLB[i]PFN0 and not TLB[i]Mask) || # Masking mplementation dependent
             TLB[i]C0 || TLB[i]D0 || TLB[i]V0 || TLB[i]G
   # if in guest mode, if the TLB entry guest id != guest id then zero the result
   if (GuestCtl0G1 = 1)
      if (GuestCtl0GM=1) and (Root.DebugDM=0) and
         (Root.StatusERL=0) and (Root.StatusEXL=0) then
             if (TLB[i]ID != GuestCtl1ID) then
                PagemaskMask = 0
                EntryHi = 0
                EntryLo1 = 0
                EntryLo0 = 0
                EntryHiEHINV = 1
             endif
      else #in root mode, RID with GuestID
         GuestCtl1RID = TLB[i]GuestID
      endif
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction