Encoding:

Format:

EVP rt

Purpose:

Enable Virtual Processor

To enable all virtual processors in a physical core other than the virtual processor that issued the instruction.

Description:

GPR[rt] = VPControl ; VPControlDIS = 0

Enabling a virtual processor means that instruction fetch is resumed.

After all other virtual processors have been enabled, VPControl_DIS is cleared. Prior to modification, if rt is nonzero, sign-extended VPControl is written to GPR[rt].If EVP is specified without rt, then rt must be 0.

See the DVP instruction to understand the application of EVP in the context of WAIT/PAUSE/external-control

("DVP" on page 246).

The execution of a DVP must be followed by the execution of an EVP. The execution of an EVP causes execution to resume immediately, where applicable, on all other virtual processors, as if the DVP had not been executed, that is, execution is completely restorable after the EVP. On the other hand, if an event occurs in between the DVP and EVP that renders state of the virtual processor UNPREDICTABLE (such as power-gating), then the effect of EVP is

UNPREDICTABLE.

EVP may only take effect if VPControl_DIS=1. Otherwise it is treated as a NOP

This instruction never executes speculatively. It must be the oldest unretired instruction to take effect.

This instruction is only available in Release 6 implementations. For implementations that do not support multithreading (Config5VP=0), this instruction must be treated as a NOP instruction.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In implementations prior to Release 6 of the architecture, this instruction resulted in a Reserved Instruction exception.

Operation:

The pseudo-code below assumes that the EVP is executed by virtual processor 0, while the target virtual processor is numbered 'n', where n is each of all remaining virtual processors.

                  if (VPControlDIS = 1)
         // Pseudo-code in italics provides recommended action wrt other VPs 
         enable_fetch(VPn) {
             if PAUSE(VPn) retires prior or at disable event
             then VPn execution is not resumed if LLbit is cleared prior to EVP
         }
         enable_interrupt(VPn) {
             if WAIT(VPn) retires prior or at disable event
             then interrupts are ignored by VPn until EVP
         }
         endif
data = VPControl
GPR[rt] = sign_extend(data)
VPControlDIS = 0

Exceptions:

Coprocessor Unusable

Reserved Instruction (pre-Release 6 implementations)

Programming Notes:

Before executing an EVP in a DVP/EVP pair, software should first read VPControl_DIS, returned by DVP, to determine whether the virtual processors are already disabled. If so, the DVP/EVP sequence should be abandoned. This step allows software to safely nest DVP/EVP pairs.

Privileged software may use DVP/EVP to disable virtual processors on a core, such as for the purpose of doing a cache flush without interference from other processes in a system with multiple virtual processors or physical cores.

DVP (and EVP) may be used in other cases such as for power-savings or changing state that is applicable to all virtual processors in a core, such as virtual processor scheduling priority, as described below:

   ll t0 0(a0)
   dvp   // disable all other virtual processors
   pause  // wait for LLbit to clear
   evp   // enable all othe virtual processors
   ll t0 0(a0)
   dvp   // disable all other virtual processors
   <change core-wide state>
   evp   // enable all othe virtual processors